专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US09337872B2 Configurable, error-tolerant memory control 有权
标题翻译：可配置的，容错的内存控制
公开(公告)号：US09337872B2
公开(公告)日：2016-05-10
申请号：US14112935
申请日：2012-03-10
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： H03M13/35 , G06F11/10 , G06F11/16
CPC分类号： H03M13/356 , G06F11/10 , G06F11/1666
摘要： Configurable, error-tolerant communication of memory control information between components of a memory system. A controller component and memory component each have a variable-width command/address (CA) interface that operates in conjunction with an error detection/correction (EDC) channel to enable a variable level of error detection and correction with respect to command/address information conveyed between the two components as the widths of the CA interfaces are adjusted.
摘要翻译：存储器系统的组件之间的可配置的，容错的通信存储器控制信息。控制器组件和存储器组件各自具有与错误检测/校正（EDC）通道一起操作的可变宽度命令/地址（CA）接口，以实现关于命令/地址信息的可变级别的错误检测和校正由于CA接口的宽度被调整，在两个部件之间传送。

2. 发明授权

US08537601B2 Memory controller with selective data transmission delay 有权
标题翻译：具有选择性数据传输延迟的存储控制器
公开(公告)号：US08537601B2
公开(公告)日：2013-09-17
申请号：US13543779
申请日：2012-07-06
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C11/24
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A DRAM controller component generates a timing signal and transmits, to a DRAM, write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sampled by the DRAM on one or more edges of the timing signal, a clock signal that requires a second time interval to propagate from the DRAM controller component to the DRAM, and a write command, associated with the write data, to be sampled by the DRAM on one or more edges of the clock signal. The DRAM controller component includes series-coupled delay elements to generate respective incrementally delayed signals, and a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval.
摘要翻译： DRAM控制器部件产生定时信号，并且向DRAM发送需要第一时间间隔从DRAM控制器部件传播到DRAM并由DRAM在定时信号的一个或多个边缘进行采样的写入数据，需要第二时间间隔从DRAM控制器部件传播到DRAM的时钟信号以及与写入数据相关联的写入命令，以由DRAM在时钟信号的一个或多个边缘上采样。 DRAM控制器组件包括串联耦合的延迟元件以产生相应的递增延迟的信号，以及多路复用器，用于选择延迟信号中的一个来对写入数据进行传输，以便写入数据的传输基于第一时间间隔和第二时间间隔。

3. 发明授权

US08261039B2 Memory controllers, methods, and systems supporting multiple memory modes 有权
标题翻译：支持多种内存模式的内存控制器，方法和系统
公开(公告)号：US08261039B2
公开(公告)日：2012-09-04
申请号：US12820973
申请日：2010-06-22
申请人： Richard E. Perego , Frederick A. Ware
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G06F13/00 , G06F13/28 , G06F3/00 , G06F5/00 , G11C7/00 , G11C29/00
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
摘要翻译：存储器系统包括具有多个存储器 - 控制器块的存储器控制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。

4. 发明授权

US08214616B2 Memory controller device having timing offset capability 有权
标题翻译：具有定时偏移能力的存储器控制器装置
公开(公告)号：US08214616B2
公开(公告)日：2012-07-03
申请号：US11754995
申请日：2007-05-29
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G06F13/36
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data suing a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.
摘要翻译：公开了一种存储器控制器。在一个特定的示例性实施例中，存储器控制器可以包括：第一发射器，用于相对于时钟信号同步地输出第一和第二写入命令;第二发射器，使用第一定时偏移来输出第一数据，使得第一数据到达第一根据与时钟信号的第一次转换相关的预定定时关系，存储器件;以及第三发送器，输出第二数据，该第二数据产生第二定时偏置，使得第二数据按照预定定时到达第二存储器件关于时钟信号的第二转换。

5. 发明授权

US08112608B2 Variable-width memory 有权
标题翻译：可变宽度内存
公开(公告)号：US08112608B2
公开(公告)日：2012-02-07
申请号：US12631614
申请日：2009-12-04
申请人： Richard E Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E Perego , Donald C. Stark , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F12/08
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described is a memory system in which the memory core organization changes with device width. The number of physical memory banks accessed reduces with device width, resulting in reduced power usage for relatively narrow memory configurations. Increasing the number of logic memory banks for narrow memory widths reduces the likelihood of bank conflicts, and consequently improves speed performance.
摘要翻译：描述了存储器系统，其中存储器核心组织随设备宽度而变化。所访问的物理存储器组的数量随着器件宽度而减少，导致相对较窄的存储器配置的功率消耗减少。增加用于窄内存宽度的逻辑内存库的数量可以减少存储体冲突的可能性，从而提高速度性能。

6. 发明申请

US20110037772A1 Scalable Unified Memory Architecture 有权
标题翻译：可扩展的统一内存架构
公开(公告)号：US20110037772A1
公开(公告)日：2011-02-17
申请号：US12911624
申请日：2010-10-25
申请人： Richard E. Perego
发明人： Richard E. Perego
IPC分类号： G06F15/167
CPC分类号： G09G5/363 , G06T1/60 , G09G5/393 , G09G2352/00 , G09G2360/125
摘要： A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instructions. The shared memory is configured to store main memory data and graphical data. Certain computing engines are capable of processing graphical data. The memory controller may include a graphics controller that provides instructions to the computing engine. An interconnect on each module allows multiple modules to be coupled to the memory controller.
摘要翻译：存储器架构包括耦合到多个模块的存储器控制器。每个模块包括耦合到共享存储器的计算引擎。每个计算引擎能够从存储器控制器接收指令并处理接收到的指令。共享内存配置为存储主内存数据和图形数据。某些计算引擎能够处理图形数据。存储器控制器可以包括向计算引擎提供指令的图形控制器。每个模块上的互连允许多个模块耦合到存储器控制器。

7. 发明授权

US07853837B2 Memory controller and method for operating a memory controller having an integrated bit error rate circuit 有权
标题翻译：用于操作具有集成误码率电路的存储器控制器的存储器控制器和方法
公开(公告)号：US07853837B2
公开(公告)日：2010-12-14
申请号：US11677843
申请日：2007-02-22
申请人： Richard E. Perego , Christopher J. Madden
发明人： Richard E. Perego , Christopher J. Madden
IPC分类号： G06F11/00 , G11C29/00 , H04W4/00 , H04B17/00
CPC分类号： G06F11/004 , G01R31/31709 , G01R31/3171 , G06F11/00 , G11C29/022
摘要： A system, among other embodiments, includes a memory controller having an integrated BER circuit and a plurality of memory devices. The memory controller also includes a control circuit and an interface having at least one transmit circuit to provide write data to at least one of the memory devices and at least one receive circuit to receive read data from at least one of the memory devices. The BER circuit includes a request generator circuit that outputs a request for a memory transaction. A request multiplexer selectively outputs a memory request to the interface from the request generator circuit or the control circuit. A data generator circuit outputs corresponding write data. A first write multiplexer selectively outputs the write data to the interface from the data generator circuit or the control circuit. A read multiplexer selectively receives read data from the receive circuit. The data generator circuit also outputs corresponding write data to a comparator circuit via a second write multiplexer. The comparator circuit outputs an error signal in response to a comparison of the received read data and corresponding stored write data. A counter outputs a count value indicating the number of errors (or bit errors) in response to the error signal. A register interface accesses the count value in the counter and a register that output one or more select signals during a mode of operation. The register interface also allows for controlling the data generator and request generator circuits.
摘要翻译：除其它实施例之外，系统包括具有集成BER电路和多个存储器件的存储器控制器。存储器控制器还包括控制电路和具有至少一个发射电路的接口，以向至少一个存储器件和至少一个接收电路提供写入数据，以从至少一个存储器件接收读取数据。 BER电路包括输出对存储器事务的请求的请求发生器电路。请求复用器从请求发生器电路或控制电路选择性地向接口输出存储器请求。数据发生器电路输出相应的写入数据。第一写入复用器选择性地将写入数据从数据发生器电路或控制电路输出到接口。读取多路复用器选择性地从接收电路接收读取数据。数据发生器电路还经由第二写复用器将对应的写数据输出到比较器电路。比较器电路响应于所接收的读取数据和对应的存储写入数据的比较而输出错误信号。计数器响应于误差信号输出指示错误数量（或位错误）的计数值。寄存器接口访问计数器中的计数值和在操作模式下输出一个或多个选择信号的寄存器。寄存器接口还允许控制数据发生器和请求发生器电路。

8. 发明授权

US07848156B2 Early read after write operation memory device, system and method 有权
标题翻译：写操作后早期读取存储器件，系统和方法
公开(公告)号：US07848156B2
公开(公告)日：2010-12-07
申请号：US12055679
申请日：2008-03-26
申请人： Richard E Perego , Frederick A Ware
发明人： Richard E Perego , Frederick A Ware
IPC分类号： G11C7/00
CPC分类号： G11C7/22 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C2207/2281 , G11C2207/229
摘要： A memory device, system and method for allowing an early read operation after one or more write operations is provided according to an embodiment of the present invention. The memory device comprises an interface for providing a first write address, a first write data, and a read address. A memory core is coupled to the interface and includes a first memory section having a first data path and a first address path and a second memory section having a second data path and a second address path. In an embodiment of the present invention, the first data and first address path is independent of the second data and second address path. The first write data is provided on the first data path responsive to the first write address being provided on the first address path while a read data is provided on the second data path responsive to the read address being provided on the second address path.
摘要翻译：根据本发明的实施例，提供了在一个或多个写入操作之后允许早期读取操作的存储器件，系统和方法。存储器件包括用于提供第一写入地址，第一写入数据和读取地址的接口。存储器核心耦合到接口并且包括具有第一数据路径和第一地址路径的第一存储器部分和具有第二数据路径和第二地址路径的第二存储器部分。在本发明的实施例中，第一数据和第一地址路径独立于第二数据和第二地址路径。响应于在第一地址路径上提供第一写地址而在第一数据路径上提供第一写入数据，同时响应于在第二地址路径上提供的读地址在第二数据路径上提供读数据。

9. 发明申请

US20100262790A1 Memory Controllers, Methods, and Systems Supporting Multiple Memory Modes 有权
标题翻译：支持多种内存模式的内存控制器，方法和系统
公开(公告)号：US20100262790A1
公开(公告)日：2010-10-14
申请号：US12820973
申请日：2010-06-22
申请人： Richard E. Perego , Frederick A. Ware
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
摘要翻译：存储器系统包括具有多个存储器 - 控制器块的存储器控制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。

10. 发明申请

US20100077267A1 Memory System with Point-to-Point Request Interconnect 有权
标题翻译：具有点对点请求的内存系统互连
公开(公告)号：US20100077267A1
公开(公告)日：2010-03-25
申请号：US12627769
申请日：2009-11-30
申请人： Richard E. Perego , Frederick A. Ware
发明人： Richard E. Perego , Frederick A. Ware
IPC分类号： G06F11/26 , G01R31/28
CPC分类号： G11C7/1072 , G06F13/1678 , G06F13/1684 , G06F13/1694 , G11C5/06 , G11C7/1045 , G11C7/1075
摘要： A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory devices, each of which includes N independently addressable memory blocks. All of the external request ports are connected to respective external request ports on the memory device or devices used in a given configuration. The number of request ports per memory device and the data width of each memory device changes with the number of memory devices such that the ratio of the request-access granularity to the data granularity remains constant irrespective of the number of memory devices.
摘要翻译：存储器系统包括具有多个存储器 - 控制器块的存储器控制器，每个存储器控制器块通过外部请求端口传送独立的事务请求。请求端口通过点对点连接耦合到一个到N个存储器件，每个存储器件包括N个可独立寻址的存储器块。所有外部请求端口都连接到存储设备上的相应外部请求端口或给定配置中使用的设备。每个存储器件的请求端口的数量和每个存储器件的数据宽度随着存储器件的数量而变化，使得请求访问粒度与数据粒度的比率保持恒定，而与存储器件的数量无关。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式