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1. 发明申请

US20060026472A1 Designing Scan Chains With Specific Parameter Sensitivities to Identify Process Defects 失效
标题翻译：设计具有特定参数敏感度的扫描链来识别过程缺陷
公开(公告)号：US20060026472A1
公开(公告)日：2006-02-02
申请号：US10710642
申请日：2004-07-27
申请人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
发明人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译：公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划决定了扫描链的数量和长度。基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

2. 发明申请

US20060036975A1 DEFECT DIAGNOSIS FOR SEMICONDUCTOR INTEGRATED CIRCUITS 失效
标题翻译：半导体集成电路缺陷诊断
公开(公告)号：US20060036975A1
公开(公告)日：2006-02-16
申请号：US10710879
申请日：2004-08-10
申请人： James Adkisson , Greg Bazan , John Cohn , Francis Gravel , Leendert Huisman , Phillip Nigh , Leah Pastel , Kenneth Rowe , Thomas Sopchak , David Sweenor
发明人： James Adkisson , Greg Bazan , John Cohn , Francis Gravel , Leendert Huisman , Phillip Nigh , Leah Pastel , Kenneth Rowe , Thomas Sopchak , David Sweenor
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/318342
摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.
摘要翻译：一种半导体芯片缺陷诊断方法。该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

3. 发明申请

US20070160920A1 METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS 有权
标题翻译：将制造监控器添加到集成电路卡的方法
公开(公告)号：US20070160920A1
公开(公告)日：2007-07-12
申请号：US11687731
申请日：2007-03-19
申请人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Thomas Sopchak , David Vallett
发明人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Thomas Sopchak , David Vallett
IPC分类号： G03F1/00 , G03C5/00 , G06F17/50
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.
摘要翻译：一种用于设计的集成电路，方法和系统以及制造集成电路的方法。该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状，集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

4. 发明申请

US20060225023A1 METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS 有权
标题翻译：将制造监控器添加到集成电路卡的方法
公开(公告)号：US20060225023A1
公开(公告)日：2006-10-05
申请号：US10907494
申请日：2005-04-04
申请人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Thomas Sopchak , David Vallett
发明人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Thomas Sopchak , David Vallett
IPC分类号： G06F17/50
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.
摘要翻译：一种用于设计的集成电路，方法和系统以及制造集成电路的方法。该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状，集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

5. 发明申请

US20080017857A1 METHOD OF ADDING FABRICATION MONITORS TO INTEGRATED CIRCUIT CHIPS 失效
标题翻译：将制造监控器添加到集成电路卡的方法
公开(公告)号：US20080017857A1
公开(公告)日：2008-01-24
申请号：US11859890
申请日：2007-09-24
申请人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Thomas Sopchak , David Vallett
发明人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Thomas Sopchak , David Vallett
IPC分类号： H01L23/58
CPC分类号： H01L22/20 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit, a method and a system for designing and a method fabricating the integrated circuit. The method including: (a) generating a photomask level design of an integrated circuit design of the integrated circuit, the photomask level design comprising a multiplicity of integrated circuit element shapes; (b) designating regions of the photomask level design between adjacent integrated circuit element shapes, the designated regions large enough to require placement of fill shapes between the adjacent integrated circuit elements based on fill shape rules, the fill shapes not required for the operation of the integrated circuit; and (c) placing one or more monitor structure shapes of a monitor structure in at least one of the designated regions, the monitor structure not required for the operation of the integrated circuit.
摘要翻译：一种用于设计的集成电路，方法和系统以及制造集成电路的方法。该方法包括：（a）生成集成电路的集成电路设计的光掩模级设计，光掩模级设计包括多个集成电路元件形状; （b）指定相邻集成电路元件形状之间的光掩模级设计的区域，指定区域足够大以至于基于填充形状规则需要在相邻集成电路元件之间放置填充形状，集成电路; 以及（c）将监视器结构的一个或多个监视器结构形状放置在指定区域中的至少一个中，该集成电路的操作不需要监视器结构。

6. 发明申请

US20050273656A1 LEARNING BASED LOGIC DIAGNOSIS 有权
标题翻译：基于学习的逻辑诊断
公开(公告)号：US20050273656A1
公开(公告)日：2005-12-08
申请号：US10709672
申请日：2004-05-21
申请人： James Adkisson , John Cohn , Leendert Huisman , Maroun Kassab , Leah Pfeifer Pastel , David Sweenor
发明人： James Adkisson , John Cohn , Leendert Huisman , Maroun Kassab , Leah Pfeifer Pastel , David Sweenor
IPC分类号： G06F11/00
CPC分类号： G06F11/2252 , G06F11/261
摘要： A system and method for diagnosing a failure in an electronic device. A disclosed system comprises: a defect table that associates previously studied features with known failures; and a fault isolation system that compares an inputted set of suspected faulty device features with the previously studied features listed in the defect table in order to identify causes of the failure.
摘要翻译：一种用于诊断电子设备故障的系统和方法。所公开的系统包括：将先前研究的特征与已知故障相关联的缺陷表; 以及故障隔离系统，其将输入的可疑故障设备特征集合与缺陷表中列出的先前研究的特征进行比较，以识别故障原因。

7. 发明申请

US20070296006A1 STRUCTURE FOR PIXEL SENSOR CELL THAT COLLECTS ELECTRONS AND HOLES 失效
标题翻译：用于收集电子和孔的像素传感器单元的结构
公开(公告)号：US20070296006A1
公开(公告)日：2007-12-27
申请号：US11850776
申请日：2007-09-06
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Mark Jaffe , Jeffrey Johnson , Alain Loiseau
IPC分类号： H01L31/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281 , H01L31/1037
摘要： The present invention relates to a design structure for a pixel sensor cell. The pixel sensor cell approximately doubles the available signal for a given quanta of light. A design structure for a pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.
摘要翻译：本发明涉及一种像素传感器单元的设计结构。像素传感器单元对于给定的光量大约使可用信号加倍。具有降低的复杂度的像素传感器单元的设计结构包括形成在基板的表面下面的n型收集阱区域，用于收集电子辐射产生的电子撞击在像素传感器单元上，以及p型收集阱区域用于收集由撞击光子产生的孔的基板的表面。具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小的第一输入和第二输入的信号。

8. 发明申请

US20070145438A1 PIXEL SENSOR CELL HAVING REDUCED PINNING LAYER BARRIER POTENTIAL AND METHOD THEREOF 有权
标题翻译：具有减少的钉扎层障碍物的像素传感器电池及其方法
公开(公告)号：US20070145438A1
公开(公告)日：2007-06-28
申请号：US11681454
申请日：2007-03-02
申请人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
发明人： James Adkisson , Andres Bryant , John Ellis-Monaghan , Jeffrey Gambino , Mark Jaffe , Jerome Lasky , Richard Phelps
IPC分类号： H01L31/113
CPC分类号： H01L27/14689 , H01L27/14603 , H01L27/14609 , H01L31/0352
摘要： A pixel sensor cell structure and method of manufacture. The pixel cell comprises a doped layer formed adjacent to a first side of a transfer gate structure for coupling a collection well region and a channel region. Potential barrier interference to charge transfer caused by a pinning layer is reduced.
摘要翻译：像素传感器单元结构及其制造方法。像素单元包括与传输栅极结构的第一侧相邻形成的用于耦合收集阱区和沟道区的掺杂层。减少了由钉扎层引起的对电荷转移的电势障碍干扰。

9. 发明申请

US20070102738A1 LIGHT SHIELD FOR CMOS IMAGER 有权
标题翻译： CMOS成像器的光栅
公开(公告)号：US20070102738A1
公开(公告)日：2007-05-10
申请号：US11164072
申请日：2005-11-09
申请人： James Adkisson , Jeffrey Gambino , Mark Jaffe
发明人： James Adkisson , Jeffrey Gambino , Mark Jaffe
IPC分类号： H01L31/113 , H01L31/062
CPC分类号： H01L27/14623 , H01L27/14685
摘要： The present invention provides a light shield for shielding the floating diffusion of a complementary metal-oxide semiconductor (CMOS) imager. In accordance with an embodiment of the present invention, there is provided a pixel sensor cell including: a device region formed on a substrate; and a first layer of material forming a sidewall adjacent to a side of the device region for blocking electromagnetic radiation from the device region.
摘要翻译：本发明提供一种用于屏蔽互补金属氧化物半导体（CMOS）成像器的浮动扩散的遮光罩。根据本发明的实施例，提供了一种像素传感器单元，包括：形成在基板上的器件区域; 以及形成与所述器件区域的一侧相邻的侧壁的第一材料层，用于阻挡来自所述器件区域的电磁辐射。

10. 发明申请

US20060128126A1 MASKED SIDEWALL IMPLANT FOR IMAGE SENSOR 有权
标题翻译：用于图像传感器的嵌入式平板植入体
公开(公告)号：US20060128126A1
公开(公告)日：2006-06-15
申请号：US10905043
申请日：2004-12-13
申请人： James Adkisson , Mark Jaffe , Arthur Johnson , Robert Leidy , Jeffrey Maling
发明人： James Adkisson , Mark Jaffe , Arthur Johnson , Robert Leidy , Jeffrey Maling
IPC分类号： H01L21/425
CPC分类号： H01L27/14643 , H01L27/1463 , H01L27/14687 , H01L27/14689
摘要： A novel image sensor structure formed on a substrate of a first conductivity type includes a photosensitive device of a second conductivity type and a surface pinning layer of the first conductivity type. A trench isolation region is formed adjacent to the photosensitive device pinning layer. The structure includes a dopant region comprising material of the first conductivity type formed along a sidewall of the isolation region that is adapted to electrically couple the pinning layer to the substrate. The corresponding method facilitates an angled ion implantation of dopant material in the isolation region sidewall by first fabricating the photoresist layer and reducing its size by removing a corner, or a corner portion thereof, which may block the angled implant material. To facilitate the angled implant to the sidewall edge past resist block masks, two methods are proposed: 1) a spacer type etch of the imaged photoresist; or, 2) a corner sputter process of the imaged photoresist.
摘要翻译：形成在第一导电类型的衬底上的新型图像传感器结构包括第二导电类型的光敏器件和第一导电类型的表面钉扎层。在光敏器件钉扎层附近形成沟槽隔离区域。该结构包括掺杂区域，该掺杂剂区域包括沿着隔离区域的侧壁形成的第一导电类型的材料，其适于将钉扎层电耦合到衬底。相应的方法通过首先制造光致抗蚀剂层并且通过去除可能阻挡成角度的植入材料的角部或其角部来减小其尺寸来促进掺杂剂材料在隔离区域侧壁中的成角度的离子注入。为了促进通过抗蚀剂阻挡掩模的侧壁边缘的成角度注入，提出了两种方法：1）成像光致抗蚀剂的间隔物型蚀刻; 或2）成像光致抗蚀剂的角溅射工艺。

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