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1. 发明申请

US20060036975A1 DEFECT DIAGNOSIS FOR SEMICONDUCTOR INTEGRATED CIRCUITS 失效
标题翻译：半导体集成电路缺陷诊断
公开(公告)号：US20060036975A1
公开(公告)日：2006-02-16
申请号：US10710879
申请日：2004-08-10
申请人： James Adkisson , Greg Bazan , John Cohn , Francis Gravel , Leendert Huisman , Phillip Nigh , Leah Pastel , Kenneth Rowe , Thomas Sopchak , David Sweenor
发明人： James Adkisson , Greg Bazan , John Cohn , Francis Gravel , Leendert Huisman , Phillip Nigh , Leah Pastel , Kenneth Rowe , Thomas Sopchak , David Sweenor
IPC分类号： G06F17/50
CPC分类号： G01R31/31718 , G01R31/318342
摘要： A method for defect diagnosis of semiconductor chip. The method comprises the steps of (a) identifying M design structures and N physical characteristics of the circuit design, wherein M and N are positive integers, wherein each design structure of the M design structures is testable as to pass or fail, and wherein each physical characteristic of the N physical characteristics is present in at least one design structure of the M design structures; (b) for each design structure of the M design structures of the circuit design, determining a fail rate and determining whether the fail rate is high or low; and (c) if every design structure of the M design structures in which a physical characteristic of the N physical characteristics is present has a high fail rate, then flagging the physical characteristic as being likely to contain at least a defect.
摘要翻译：一种半导体芯片缺陷诊断方法。该方法包括以下步骤：（a）识别电路设计的M个设计结构和N个物理特性，其中M和N是正整数，其中M个设计结构的每个设计结构可以通过或失败，并且其中每个 N物理特性的物理特性存在于M设计结构的至少一个设计结构中; （b）对于电路设计的M设计结构的每个设计结构，确定故障率并确定故障率是高还是低; 和（c）如果存在N个物理特性的物理特性的M设计结构的每个设计结构具有高故障率，则将物理特性标记为可能至少包含缺陷。

2. 发明申请

US20060026472A1 Designing Scan Chains With Specific Parameter Sensitivities to Identify Process Defects 失效
标题翻译：设计具有特定参数敏感度的扫描链来识别过程缺陷
公开(公告)号：US20060026472A1
公开(公告)日：2006-02-02
申请号：US10710642
申请日：2004-07-27
申请人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
发明人： James Adkisson , Greg Bazan , John Cohn , Matthew Grady , Leendert Huisman , Mark Jaffe , Phillip Nigh , Leah Pastel , Thomas Sopchak , David Sweenor , David Vallett
IPC分类号： G06F17/50 , G01R31/28
CPC分类号： G06F17/5045 , G01R31/31855 , G01R31/318586 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for designing scan chains in an integrated circuit chip with specific parameter sensitivities to identify fabrication process defects causing test fails and chip yield loss. The composition of scan paths in the integrated circuit chip is biased to allow them to also function as on-product process monitors. The method adds grouping constraints that bias scan chains to have common latch cell usage where possible, and also biases cell routing to constrain scan chain routing to given restricted metal layers for interconnects. The method assembles a list of latch design parameters which are sensitive to process variation or integrity, and formulates a plan for scan chain design which determines the number and the length of scan chains. A model is formulated of scan chain design based upon current state of yield and process integrity, wherein certain latch designs having dominant sensitivities are chosen for specific ones of the scan chains on the chip. The model is provided as input parameters to a global placement and wiring program used to lay out the scan chains. Test data on the chip is then analyzed to determine and isolate systematic yield problems denoted by attributes of a statistically significant failing population of a specific type of scan chain.
摘要翻译：公开了一种用于设计具有特定参数灵敏度的集成电路芯片中的扫描链的方法，以识别导致测试失败和芯片产量损失的制造工艺缺陷。集成电路芯片中的扫描路径的组成被偏置以允许它们也用作产品过程监视器。该方法增加了分组约束，使得扫描链偏置以在可能的情况下具有共同的锁存单元使用，并且还偏置小区路由以将扫描链路由限制到用于互连的给定受限金属层。该方法组合了对过程变化或完整性敏感的锁存器设计参数列表，并且制定了扫描链设计的计划，该计划决定了扫描链的数量和长度。基于产量和过程完整性的当前状态来制定扫描链设计的模型，其中为芯片上的特定扫描链选择具有主要灵敏度的某些锁存器设计。该模型作为输入参数提供给用于布置扫描链的全局放置和布线程序。然后对芯片上的测试数据进行分析，以确定和分离由特定类型的扫描链的统计学显着失败群体的属性表示的系统产量问题。

3. 发明申请

US20060022693A1 CIRCUIT AND METHOD FOR MONITORING DEFECTS 失效
标题翻译：用于监测缺陷的电路和方法
公开(公告)号：US20060022693A1
公开(公告)日：2006-02-02
申请号：US10710640
申请日：2004-07-27
申请人： Greg Bazan , John Cohn , Matthew Grady , Phillip Nigh , Leah Pastel , Thomas Sopchak
发明人： Greg Bazan , John Cohn , Matthew Grady , Phillip Nigh , Leah Pastel , Thomas Sopchak
IPC分类号： G01R31/26
CPC分类号： H01L22/34 , G01R31/31855 , H01L2924/0002 , H01L2924/00
摘要： A circuit and a method for monitoring defects in an integrated circuit chip. The circuit including a defect monitor portion and a sense element portion, the defect monitor portion either coupled to inputs of sense elements arranged in a chain or coupled between sense elements and forming portions of the chain.
摘要翻译：用于监测集成电路芯片中的缺陷的电路和方法。所述电路包括缺陷监测部分和感测元件部分，所述缺陷监测部分耦合到布置在链中的感测元件的输入或耦合在感测元件和链的形成部分之间。

4. 发明申请

US20050282297A1 METHOD AND STRUCTURE FOR DEFECT MONITORING OF SEMICONDUCTOR DEVICES USING POWER BUS WIRING GRIDS 失效
标题翻译：使用电力总线接线网的半导体器件缺陷监测的方法和结构
公开(公告)号：US20050282297A1
公开(公告)日：2005-12-22
申请号：US10710114
申请日：2004-06-18
申请人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
发明人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
IPC分类号： G01R31/28 , G01R31/307 , H01L21/00 , H01L23/544
CPC分类号： G01R31/2884 , G01R31/307 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.
摘要翻译：用于实现集成电路的缺陷检查的方法包括在第一金属互连级上配置电力总线栅格结构，所述电力总线栅格结构包括第一多个线对。第一组多个线对被布置成使得第一多个线对中的每一个中的第一线电耦合到第一金属互连水平面下方的导电结构，并且在第一多个线中的每一个中的第二线对最初与第一金属互连级别下方的导电结构电隔离。第一多个线对中的每一个中的第一线被偏置到已知电压，并且在第一多个线对中的每一个的第一线和第二线之间执行电荷对比度检查。

5. 发明申请

US20060066342A1 Utilizing clock shield as defect monitor 失效
公开(公告)号：US20060066342A1
公开(公告)日：2006-03-30
申请号：US11280008
申请日：2005-11-16
申请人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
发明人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
IPC分类号： G01R31/26
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.

6. 发明申请

US20060170104A1 METHOD AND STRUCTURE FOR DEFECT MONITORING OF SEMICONDUCTOR DEVICES USING POWER BUS WIRING GRIDS 失效
标题翻译：使用电力总线接线网的半导体器件缺陷监测的方法和结构
公开(公告)号：US20060170104A1
公开(公告)日：2006-08-03
申请号：US11277663
申请日：2006-03-28
申请人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
发明人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
IPC分类号： H01L23/52
CPC分类号： G01R31/2884 , G01R31/307 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A method for implementing defect inspection of an integrated circuit includes configuring a power bus grid structure on a first metal interconnect level, the power bus grid structure including a first plurality of wire pairs. The first plurality of wire pairs is arranged in a manner such that a first wire in each of the first plurality of wire pairs is electrically coupled to conductive structures beneath the first metal interconnect level, and a second wire in each of the first plurality of wire pairs is initially electrically isolated from the conductive structures beneath the first metal interconnect level. The first wire in each of the first plurality of wire pairs is biased to a known voltage, and a charge contrast inspection is performed between the first wire and the second wire of each of the first plurality of wire pairs.
摘要翻译：用于实现集成电路的缺陷检查的方法包括在第一金属互连级上配置电力总线栅格结构，所述电力总线栅格结构包括第一多个线对。第一组多个线对被布置成使得第一多个线对中的每一个中的第一线电耦合到第一金属互连水平面下方的导电结构，并且在第一多个线中的每个中的第二线对最初与第一金属互连级别下方的导电结构电隔离。第一多个线对中的每一个中的第一线被偏置到已知电压，并且在第一多个线对中的每一个的第一线和第二线之间执行电荷对比度检查。

7. 发明申请

US20070108964A1 UTILIZING CLOCK SHIELD AS DEFECT MONITOR 失效
标题翻译：使用时钟屏蔽作为缺陷监视器
公开(公告)号：US20070108964A1
公开(公告)日：2007-05-17
申请号：US11382601
申请日：2006-05-10
申请人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
发明人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
IPC分类号： G01R31/28
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.
摘要翻译：公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。屏蔽与时钟信号接线相邻，接地线将屏蔽接地。屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

8. 发明申请

US20050285611A1 UTILIZING CLOCK SHIELD AS DEFECT MONITOR 有权
标题翻译：使用时钟屏蔽作为缺陷监视器
公开(公告)号：US20050285611A1
公开(公告)日：2005-12-29
申请号：US10710222
申请日：2004-06-28
申请人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
发明人： John Cohn , Leah Pastel , Thomas Sopchak , David Vallett
IPC分类号： G01R31/02 , G01R31/26 , G01R31/30 , G01R31/317
CPC分类号： G01R31/31727 , G01R31/025 , G01R31/30 , G01R31/31725
摘要： Disclosed is a shielded clock tree that has one or more clock signal buffers and clock signal splitters, with clock signal wiring connecting the clock signal buffers to the clock signal splitters. Shielding is adjacent the clock signal wiring, where ground wiring connects the shielding to ground. The shielding comprises shield wires positioned adjacent and parallel to the clock signal wiring. The invention provides switches in the ground wiring, and these switches are connected to, and controlled by, a test controller.
摘要翻译：公开了具有一个或多个时钟信号缓冲器和时钟信号分离器的屏蔽时钟树，时钟信号将时钟信号缓冲器连接到时钟信号分离器。屏蔽与时钟信号接线相邻，接地线将屏蔽接地。屏蔽包括与时钟信号布线相邻并且平行的屏蔽线。本发明提供接地布线中的开关，并且这些开关连接到测试控制器并由其控制。

9. 发明申请

US20050138508A1 SCAN CHAIN DIAGNOSTICS USING LOGIC PATHS 有权
标题翻译：使用LOGIC PATHS扫描链诊断
公开(公告)号：US20050138508A1
公开(公告)日：2005-06-23
申请号：US10707373
申请日：2003-12-09
申请人： Leendert Huisman , Leah Pastel
发明人： Leendert Huisman , Leah Pastel
IPC分类号： G01R31/3185 , G11B20/18 , G11B5/00 , G01R31/28 , G06K5/04 , G11B20/20
CPC分类号： G01R31/318566 , G11B20/1816
摘要： A structure and method for performing scan chain diagnosis. The structure comprises a diagnosed/target scan chain and one or more good observation scan chains. Observing logic paths from the target scan chain to observation scan chains can be identified according to a pre-specified criterion. The diagnosed scan chain is loaded in series with a test pattern. Then, the contents of the observed latch(es) in the diagnosed scan chain propagate through the observing logic paths. Then, the output signals of the observing logic paths are strobed into the observing latch(es) in the observing scan chain(s). Then, the observing scan chain(s) are unloaded and the contents of the observing latch(es) are collected and analyzed to determine the defect types and the defect ranges in the diagnosed scan chain.
摘要翻译：用于执行扫描链诊断的结构和方法。该结构包括诊断/目标扫描链和一个或多个良好的观察扫描链。可以根据预先指定的标准来识别从目标扫描链到观察扫描链的逻辑路径。诊断的扫描链与测试图案串联加载。然后，诊断的扫描链中观察到的锁存器的内容通过观察逻辑路径传播。然后，观测逻辑路径的输出信号被选通到观测扫描链中的观测锁存器中。然后，观察扫描链被卸载，并且收集和分析观察锁存器的内容以确定诊断的扫描链中的缺陷类型和缺陷范围。

10. 发明申请

US20060071208A1 INSPECTION METHODS AND STRUCTURES FOR VISUALIZING AND/OR DETECTING SPECIFIC CHIP STRUCTURES 有权
标题翻译：用于可视化和/或检测特定芯片结构的检查方法和结构
公开(公告)号：US20060071208A1
公开(公告)日：2006-04-06
申请号：US10711765
申请日：2004-10-04
申请人： Jerome Cann , Steven Holmes , Leendert Huisman , Cherie Kagan , Leah Pastel , Paul Pastel , James Salimeno , David Vallett
发明人： Jerome Cann , Steven Holmes , Leendert Huisman , Cherie Kagan , Leah Pastel , Paul Pastel , James Salimeno , David Vallett
IPC分类号： H01L23/58 , H01L21/66
CPC分类号： H01L21/7684 , H01L21/3212 , H01L21/76843 , H01L21/76865 , H01L21/7688
摘要： The present invention provides inspection methods and structures for facilitating the visualization and/or detection of specific chip structures. Optical or fluorescent labeling techniques are used to “stain” a specific chip structure for easier detection of the structure. Also, a temporary/sacrificial illuminating (e.g., fluorescent) film is added to the semiconductor process to facilitate the detection of a specific chip structure. Further, a specific chip structure is doped with a fluorescent material during the semiconductor process. A method of the present invention comprises: providing a first and a second material; processing the first material to form a portion of a semiconductor structure; and detecting a condition of the second material to determine whether processing of the first material is complete.
摘要翻译：本发明提供了用于促进特定芯片结构的可视化和/或检测的检查方法和结构。光学或荧光标记技术用于“污染”特定的芯片结构，以便于检测结构。此外，向半导体工艺中添加临时/牺牲照明（例如荧光）膜以便于检测特定的芯片结构。此外，在半导体工艺期间，用荧光材料掺杂特定的芯片结构。本发明的方法包括：提供第一和第二材料; 处理所述第一材料以形成半导体结构的一部分; 以及检测所述第二材料的状态以确定所述第一材料的处理是否完成。

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