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    • 3. 发明申请
    • Method for manufacturing microfluidic chip with electroosmotic flow controlled by inducing electric field through self-assembled monolayer
    • 通过自组装单层诱导电场控制电渗流的微流控芯片的制造方法
    • US20050087444A1
    • 2005-04-28
    • US10690509
    • 2003-10-23
    • Hsien-Chang ChangChing-Chou WuRen-Guen Wu
    • Hsien-Chang ChangChing-Chou WuRen-Guen Wu
    • B01L3/00C25B15/00F04B19/00G01N27/447
    • B82Y30/00B01L3/502707B01L3/50273B01L2200/12B01L2400/0418B82Y40/00F04B19/006G01N27/44752
    • A method for manufacturing a microfluidic chip with electroosmotic flow (EOF) controlled by inducing a perpendicularly electric field through a self-assembled monolayer (SAM) is disclosed. The method is primarily to combine a top plate and a bottom plate; wherein the bottom plate has a gate electrode on an upper surface thereof and has the SAM formed on said gate electrode. The top plate has an elongate micro channel groove which is narrower than that of the gate electrode, recessed in a lower portion thereof and filled with a buffer solution. Accordingly, the flowing direction and the flowing velocity of said EOF are controlled by supplying high voltage to two ends of said micro channel groove to produce an electric field for driving EOF and supplying an inducing voltage to the gate electrode. The SAM of the present invention can be easily formed and thin enough to lower the inducing voltage required for controlling the zeta potential and have a smaller chip size. Furthermore, direction and velocity of the EOF can be controlled regardless of the acidic or neutral solution filled in the channel.
    • 公开了一种制造通过自组装单层(SAM)诱导垂直电场控制的电渗流(EOF)的微流控芯片的方法。 该方法主要是结合顶板和底板; 其中所述底板在其上表面上具有栅电极,并且所述SAM形成在所述栅电极上。 顶板具有细长的微沟槽,其窄于栅极电极的凹槽,并在其下部填充缓冲溶液。 因此,所述EOF的流动方向和流动速度通过向所述微通道沟槽的两端供给高电压来产生驱动EOF的电场并向栅电极提供感应电压来控制。 本发明的SAM可以容易地形成和足够薄以降低控制ζ电位所需的感应电压并具有更小的芯片尺寸。 此外,无论在通道中填充的酸性或中性溶液如何,都可以控制EOF的方向和速度。
    • 5. 发明授权
    • Method to scale down IC layout
    • 缩小IC布局的方法
    • US08614496B2
    • 2013-12-24
    • US13347711
    • 2012-01-11
    • Hsien-Chang Chang
    • Hsien-Chang Chang
    • H01L21/70
    • G06F17/5068
    • A method scales down an integrated circuit layout structure without substantially jeopardizing electronic characteristics of devices. First, a conductive line set includes a first conductive line and a second conductive line respectively passing through a first region and a second region. Second, a sizing-down operation is performed so that the first conductive line and the second conductive line respectively have a first region scaled-down line width, a first region scaled-down space and a first region scaled-down pitch in the first region as well as selectively have a second region original line width, a second region scaled-down space and a second region scaled-down pitch in the second region. The first region scaled-down line width and the second region original line width are substantially different from each other.
    • 一种方法可以缩小集成电路布局结构,而不会基本上危及设备的电子特性。 首先,导线组包括分别通过第一区域和第二区域的第一导线和第二导线。 其次,执行施胶操作,使得第一导电线和第二导线在第一区域中分别具有第一区域缩小线宽度,第一区域缩小空间和第一区域缩小间距 以及在第二区域中选择性地具有第二区域原始线宽度,第二区域缩小空间和第二区域缩小间距。 第一区域缩小线宽度和第二区域原始线宽度彼此大不相同。
    • 6. 发明申请
    • MICROBIAL IDENTIFICATION AND MANIPULATION OF NANOSCALE BIOMOLECULES
    • 纳米生物分子的微生物鉴定和操作
    • US20120292184A1
    • 2012-11-22
    • US13108216
    • 2011-05-16
    • I-Fang CHENGHsien-Chang ChangCheng-Che Chung
    • I-Fang CHENGHsien-Chang ChangCheng-Che Chung
    • G01N27/447C25B15/00B82Y40/00
    • C12Q1/6816B03C5/005B03C5/026C12N13/00G01N33/536G01N33/558G01N33/569G01N33/582G01N33/583C12Q2565/629
    • A method of microbial identification is disclosed. The method includes the steps of assembling dielectrophoretic particles modified with specific DNA probes on a surface thereof in a continuous fluid at a predetermined location in a microchannel to form a particle assembly by a negative dielectrophoretic force and a hydrodynamic force provided by the continuous fluid, narrowing gaps between the dielectrophoretic particles of the particle assembly to enhance the electric field in the gaps between the dielectrophoretic particles, injecting a fluid containing target DNAs of a target microbe into the microchannel at a predetermined flow rate to move the target DNAs toward the particle assembly and generating a positive dielectrophoretic force by the enhanced electric field to attract the target DNAs toward the dielectrophoretic particles of the particle assembly for hybridization with the DNA probes. The present invention also discloses a method of manipulation of nanoscale biomolecules.
    • 公开了一种微生物识别方法。 该方法包括以下步骤:在微通道中的预定位置处将表面上的特定DNA探针修饰的介电泳细粒组装在微通道中的预定位置处,以通过负介电电泳力和由连续流体提供的流体动力力形成粒子组件 颗粒组件的介电电泳颗粒之间的间隙以增强介电电泳颗粒之间的间隙中的电场,以预定流速将含有目标微生物的目标DNA的流体注入微通道以将靶DNA移动到颗粒组件,并且 通过增强的电场产生正的介电电泳力,以将靶DNA吸引到颗粒组件的介电电泳颗粒,以与DNA探针杂交。 本发明还公开了一种操作纳米尺度生物分子的方法。
    • 7. 发明授权
    • Method of reducing charging damage to integrated circuits during semiconductor manufacturing
    • 在半导体制造过程中减少集成电路的充电损坏的方法
    • US07344963B2
    • 2008-03-18
    • US11379380
    • 2006-04-20
    • Hsien-Chang ChangChia-Hsin HouTsu-Yu ChuKo-Ting Chen
    • Hsien-Chang ChangChia-Hsin HouTsu-Yu ChuKo-Ting Chen
    • H01L21/425H01L29/167
    • H01L21/266H01L21/823418H01L21/823481H01L27/0207
    • A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.
    • 提供具有被划线通道包围的集成电路管芯区域的半导体衬底。 在集成电路管芯区域内,在半导体衬底上形成第一沟槽隔离区域和第二沟槽隔离区域,其中第一沟槽隔离区域将第一有源器件区域与第二有源器件区域隔离,第二沟槽隔离区域 包括用于减小负载效应的多个沟槽虚拟特征。 在第一有源器件区上形成第一栅电极,在第二有源器件区上形成第二栅电极。 第一有源器件区域被掩蔽,而第二有源器件区域和沟槽虚拟特征被暴露。 然后执行离子注入工艺以将掺杂剂物质注入到第二有源器件区域中。