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1. 发明申请

US20060270071A1 METHOD OF REDUCING CHARGING DAMAGE TO INTEGRATED CIRCUITS DURING SEMICONDUCTOR MANUFACTURING 有权
标题翻译：在半导体制造过程中减少对集成电路充电损伤的方法
公开(公告)号：US20060270071A1
公开(公告)日：2006-11-30
申请号：US11379380
申请日：2006-04-20
申请人： Hsien-Chang Chang , Chia-Hsin Hou , Tsu-Yu Chu , Ko-Ting Chen
发明人： Hsien-Chang Chang , Chia-Hsin Hou , Tsu-Yu Chu , Ko-Ting Chen
IPC分类号： H01L21/66
CPC分类号： H01L21/266 , H01L21/823418 , H01L21/823481 , H01L27/0207
摘要： A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.
摘要翻译：提供具有被划线通道包围的集成电路管芯区域的半导体衬底。在集成电路管芯区域内，在半导体衬底上形成第一沟槽隔离区域和第二沟槽隔离区域，其中第一沟槽隔离区域将第一有源器件区域与第二有源器件区域隔离，第二沟槽隔离区域包括用于减小负载效应的多个沟槽虚拟特征。在第一有源器件区上形成第一栅电极，在第二有源器件区上形成第二栅电极。第一有源器件区域被掩蔽，而第二有源器件区域和沟槽虚拟特征被暴露。然后执行离子注入工艺以将掺杂剂物质注入到第二有源器件区域中。

2. 发明授权

US07344963B2 Method of reducing charging damage to integrated circuits during semiconductor manufacturing 有权
标题翻译：在半导体制造过程中减少集成电路的充电损坏的方法
公开(公告)号：US07344963B2
公开(公告)日：2008-03-18
申请号：US11379380
申请日：2006-04-20
申请人： Hsien-Chang Chang , Chia-Hsin Hou , Tsu-Yu Chu , Ko-Ting Chen
发明人： Hsien-Chang Chang , Chia-Hsin Hou , Tsu-Yu Chu , Ko-Ting Chen
IPC分类号： H01L21/425 , H01L29/167
CPC分类号： H01L21/266 , H01L21/823418 , H01L21/823481 , H01L27/0207
摘要： A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.
摘要翻译：提供具有被划线通道包围的集成电路管芯区域的半导体衬底。在集成电路管芯区域内，在半导体衬底上形成第一沟槽隔离区域和第二沟槽隔离区域，其中第一沟槽隔离区域将第一有源器件区域与第二有源器件区域隔离，第二沟槽隔离区域包括用于减小负载效应的多个沟槽虚拟特征。在第一有源器件区上形成第一栅电极，在第二有源器件区上形成第二栅电极。第一有源器件区域被掩蔽，而第二有源器件区域和沟槽虚拟特征被暴露。然后执行离子注入工艺以将掺杂剂物质注入到第二有源器件区域中。

3. 发明授权

US07537865B2 Method of adjusting size of photomask pattern 有权
标题翻译：调整光掩模图案尺寸的方法
公开(公告)号：US07537865B2
公开(公告)日：2009-05-26
申请号：US11375408
申请日：2006-03-13
申请人： Chia-Hsin Hou , Tsu-Yu Chu
发明人： Chia-Hsin Hou , Tsu-Yu Chu
IPC分类号： G03F1/00 , G06F17/50 , G06K9/00
CPC分类号： G03F1/68
摘要： A method of adjusting the size of a photomask pattern is provided. First, the original coordinate is converted. Then the length and width of the original pattern are converted. Next, the size difference caused by the coordinate conversion is corrected according to the result of the length and width conversion.
摘要翻译：提供了调整光掩模图案尺寸的方法。首先，原始坐标被转换。然后转换原始图案的长度和宽度。接下来，根据长度和宽度转换的结果来校正由坐标转换引起的尺寸差异。

4. 发明申请

US20070212616A1 Method of adjusting size of photomask pattern 有权
标题翻译：调整光掩模图案尺寸的方法
公开(公告)号：US20070212616A1
公开(公告)日：2007-09-13
申请号：US11375408
申请日：2006-03-13
申请人： Chia-Hsin Hou , Tsu-Yu Chu
发明人： Chia-Hsin Hou , Tsu-Yu Chu
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/68
摘要： A method of adjusting the size of a photomask pattern is provided. First, the original coordinate is converted. Then the length and width of the original pattern are converted. Next, the size difference caused by the coordinate conversion is corrected according to the result of the length and width conversion.
摘要翻译：提供了调整光掩模图案尺寸的方法。首先，原始坐标被转换。然后转换原始图案的长度和宽度。接下来，根据长度和宽度转换的结果来校正由坐标转换引起的尺寸差异。

5. 发明授权

US06346366B1 Method for making an advanced guard ring for stacked film using a novel mask design 有权
标题翻译：使用新颖的面膜设计制作叠层薄膜的高级保护环的方法
公开(公告)号：US06346366B1
公开(公告)日：2002-02-12
申请号：US09596906
申请日：2000-06-19
申请人： Tsu-Yu Chu , Yi-Tung Yen , Chai-Der Chang
发明人： Tsu-Yu Chu , Yi-Tung Yen , Chai-Der Chang
IPC分类号： G03C500
CPC分类号： H01L21/765 , H01L27/10873 , H01L27/10894
摘要： A method for making advanced guard rings in a stacked film on logic/merged DRAM circuits using a novel mask design is achieved. After forming a patterned amorphous silicon (a-Si) layer that has blanket portions over the logic region, a stacked film is deposited over the a-Si layer and extending over the edge and on the memory region. A first photoresist etch mask is used to pattern FET gate electrodes in the stacked film, and the etch mask includes a portion having a minimum width W over the edge of the a-Si layer to form a wide guard ring. This wide guard ring replaces a narrow guard ring that inadvertently forms during conventional processing and that is susceptible to peeling and particle contamination of the wafer. A second photoresist etch mask is used to pattern the a-Si layer to form FET gate electrodes over the logic region. The remaining process steps commonly practiced in the industry are carried out to complete the logic/merged DRAM circuit without the peeling and contamination that results from a narrow guard ring.
摘要翻译：实现了使用新颖的掩模设计在逻辑/合并的DRAM电路上在堆叠膜中制造高级保护环的方法。在形成在逻辑区域上具有覆盖部分的图案化非晶硅（a-Si）层之后，堆叠的膜沉积在a-Si层上并在边缘和存储区上延伸。使用第一光致抗蚀剂蚀刻掩模来对层叠膜中的FET栅电极进行图案化，并且蚀刻掩模包括在a-Si层的边缘上具有最小宽度W的部分以形成宽的保护环。这种宽保护环代替了常规加工过程中无意中形成的狭窄保护环，并且易受到晶片剥落和颗粒污染。使用第二光致抗蚀剂蚀刻掩模来图案化a-Si层以在逻辑区域上形成FET栅电极。执行在工业中通常实施的其余工艺步骤来完成逻辑/合并的DRAM电路，而不会由窄的保护环产生的剥离和污染。

6. 发明授权

US06396567B1 Method and apparatus for controlling the dose of radiations applied to a semiconductor wafer during photolithography 有权
标题翻译：用于控制在光刻期间施加到半导体晶片的辐射剂量的方法和装置
公开(公告)号：US06396567B1
公开(公告)日：2002-05-28
申请号：US09324129
申请日：1999-06-02
申请人： Tsu-Yu Chu , I-Chung Chang , Kun-Pi Cheng
发明人： Tsu-Yu Chu , I-Chung Chang , Kun-Pi Cheng
IPC分类号： G03B2772
CPC分类号： G03F7/70058 , G03F7/70066 , G03F7/70075 , G03F7/70191 , G03F7/70358 , G03F7/70558
摘要： The two dimensional intensity profile of radiation applied to a semiconductor wafer during photolithography is controlled by passing the radiation beam through an attenuating member before the beam is imaged by a mask onto the wafer. The attenuating member is preferably ring shaped and is formed of a semi-transparent material such as Mo Bi Si O4, or a material that is partially reflective of the radiation.
摘要翻译：在光刻期间施加到半导体晶片的辐射的二维强度分布通过在通过掩模将光束成像到晶片之前使辐射束通过衰减部件来控制。衰减构件优选为环形，并且由诸如Mo Bi Si O 4的半透明材料或部分反射辐射的材料形成。

7. 发明授权

US5843600A Use of sub divided pattern for alignment mark recovery after inter-level dielectric planarization 失效
标题翻译：在层间电介质平坦化之后使用子分割图案进行对准标记恢复
公开(公告)号：US5843600A
公开(公告)日：1998-12-01
申请号：US901168
申请日：1997-07-28
申请人： Tsu-Yu Chu , Jui-Yu Chang , Kun-Pi Cheng
发明人： Tsu-Yu Chu , Jui-Yu Chang , Kun-Pi Cheng
IPC分类号： G03F1/00 , G03F7/00 , G03F9/00
CPC分类号： G03F9/70 , G03F1/42 , G03F7/0035 , Y10S148/102 , Y10S438/975
摘要： A mask, which does not require additional reticles, and a method of using the mask for recovering alignment marks in a wafer after an inter-level dielectric layer has been planarized and a second layer of metal has been deposited on the planarized inter-level dielectric layer are described. An alignment mark protection pattern and a clearout window pattern are sub-divided so they can be formed from a first and a second mask element. These mask elements can be formed in the peripheral region of the reticle used to pattern the device region of the wafer. The mask elements are used to expose the alignment mark protection pattern in a first layer of photoresist and the clearout window pattern in a second layer of photoresist.
摘要翻译：不需要额外的掩模版的掩模，以及在层间电介质层已被平坦化之后使用掩模来恢复晶片中的对准标记的方法，并且第二层金属已沉积在平坦化的层间电介质上描述层。对准标记保护图案和清晰窗口图案被细分，使得它们可以由第一和第二掩模元件形成。这些掩模元件可以形成在用于对晶片的器件区域进行图案化的掩模版的周边区域中。掩模元件用于在光致抗蚀剂的第一层中曝光对准标记保护图案，并在第二层光致抗蚀剂中露出清漆窗口图案。

8. 发明授权

US5902707A Mask containing alignment mark protection pattern 失效
标题翻译：面膜含有对准标记保护图案
公开(公告)号：US5902707A
公开(公告)日：1999-05-11
申请号：US118035
申请日：1998-07-17
申请人： Tsu-Yu Chu , Jui-Yu Chang , Kun-Pi Cheng
发明人： Tsu-Yu Chu , Jui-Yu Chang , Kun-Pi Cheng
IPC分类号： G03F1/00 , G03F7/00 , G03F9/00
CPC分类号： G03F9/70 , G03F1/42 , G03F7/0035 , Y10S148/102 , Y10S438/975
摘要： A mask, which does not require additional reticles, and a method of using the mask for recovering alignment marks in a wafer after an inter-level dielectric layer has been planarized and a second layer of metal has been deposited on the planarized inter-level dielectric layer are described. An alignment mark protection pattern and a clearout window pattern are sub-divided so they can be formed from a first and a second mask element. These mask elements can be formed in the peripheral region of the reticle used to pattern the device region of the wafer. The mask elements are used to expose the alignment mark protection pattern in a first layer of photoresist and the clearout window pattern in a second layer of photoresist.
摘要翻译：不需要额外的掩模版的掩模，以及在层间电介质层已被平坦化之后使用掩模来恢复晶片中的对准标记的方法，并且第二层金属已沉积在平坦化的层间电介质上描述层。对准标记保护图案和清晰窗口图案被细分，使得它们可以由第一和第二掩模元件形成。这些掩模元件可以形成在用于对晶片的器件区域进行图案化的掩模版的周边区域中。掩模元件用于在光致抗蚀剂的第一层中曝光对准标记保护图案，并在第二层光致抗蚀剂中露出清漆窗口图案。

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