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1. 发明申请

US20060270071A1 METHOD OF REDUCING CHARGING DAMAGE TO INTEGRATED CIRCUITS DURING SEMICONDUCTOR MANUFACTURING 有权
标题翻译：在半导体制造过程中减少对集成电路充电损伤的方法
公开(公告)号：US20060270071A1
公开(公告)日：2006-11-30
申请号：US11379380
申请日：2006-04-20
申请人： Hsien-Chang Chang , Chia-Hsin Hou , Tsu-Yu Chu , Ko-Ting Chen
发明人： Hsien-Chang Chang , Chia-Hsin Hou , Tsu-Yu Chu , Ko-Ting Chen
IPC分类号： H01L21/66
CPC分类号： H01L21/266 , H01L21/823418 , H01L21/823481 , H01L27/0207
摘要： A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.
摘要翻译：提供具有被划线通道包围的集成电路管芯区域的半导体衬底。在集成电路管芯区域内，在半导体衬底上形成第一沟槽隔离区域和第二沟槽隔离区域，其中第一沟槽隔离区域将第一有源器件区域与第二有源器件区域隔离，第二沟槽隔离区域包括用于减小负载效应的多个沟槽虚拟特征。在第一有源器件区上形成第一栅电极，在第二有源器件区上形成第二栅电极。第一有源器件区域被掩蔽，而第二有源器件区域和沟槽虚拟特征被暴露。然后执行离子注入工艺以将掺杂剂物质注入到第二有源器件区域中。

2. 发明授权

US07344963B2 Method of reducing charging damage to integrated circuits during semiconductor manufacturing 有权
标题翻译：在半导体制造过程中减少集成电路的充电损坏的方法
公开(公告)号：US07344963B2
公开(公告)日：2008-03-18
申请号：US11379380
申请日：2006-04-20
申请人： Hsien-Chang Chang , Chia-Hsin Hou , Tsu-Yu Chu , Ko-Ting Chen
发明人： Hsien-Chang Chang , Chia-Hsin Hou , Tsu-Yu Chu , Ko-Ting Chen
IPC分类号： H01L21/425 , H01L29/167
CPC分类号： H01L21/266 , H01L21/823418 , H01L21/823481 , H01L27/0207
摘要： A semiconductor substrate having an integrated circuit die area surrounded by a scribe lane is provided. Within the integrated circuit die area, a first trench isolation region and a second trench isolation region are formed on the semiconductor substrate, wherein the first trench isolation region isolates a first active device region from a second active device region, and the second trench isolation region comprises a plurality of trench dummy features for reducing loading effect. A first gate electrode is formed on the first active device region and a second gate electrode on the second active device region. The first active device region is masked, while the second active device region and the trench dummy features are exposed. An ion implantation process is then performed to implant dopant species into the second active device region.
摘要翻译：提供具有被划线通道包围的集成电路管芯区域的半导体衬底。在集成电路管芯区域内，在半导体衬底上形成第一沟槽隔离区域和第二沟槽隔离区域，其中第一沟槽隔离区域将第一有源器件区域与第二有源器件区域隔离，第二沟槽隔离区域包括用于减小负载效应的多个沟槽虚拟特征。在第一有源器件区上形成第一栅电极，在第二有源器件区上形成第二栅电极。第一有源器件区域被掩蔽，而第二有源器件区域和沟槽虚拟特征被暴露。然后执行离子注入工艺以将掺杂剂物质注入到第二有源器件区域中。

3. 发明授权

US07537865B2 Method of adjusting size of photomask pattern 有权
标题翻译：调整光掩模图案尺寸的方法
公开(公告)号：US07537865B2
公开(公告)日：2009-05-26
申请号：US11375408
申请日：2006-03-13
申请人： Chia-Hsin Hou , Tsu-Yu Chu
发明人： Chia-Hsin Hou , Tsu-Yu Chu
IPC分类号： G03F1/00 , G06F17/50 , G06K9/00
CPC分类号： G03F1/68
摘要： A method of adjusting the size of a photomask pattern is provided. First, the original coordinate is converted. Then the length and width of the original pattern are converted. Next, the size difference caused by the coordinate conversion is corrected according to the result of the length and width conversion.
摘要翻译：提供了调整光掩模图案尺寸的方法。首先，原始坐标被转换。然后转换原始图案的长度和宽度。接下来，根据长度和宽度转换的结果来校正由坐标转换引起的尺寸差异。

4. 发明申请

US20070212616A1 Method of adjusting size of photomask pattern 有权
标题翻译：调整光掩模图案尺寸的方法
公开(公告)号：US20070212616A1
公开(公告)日：2007-09-13
申请号：US11375408
申请日：2006-03-13
申请人： Chia-Hsin Hou , Tsu-Yu Chu
发明人： Chia-Hsin Hou , Tsu-Yu Chu
IPC分类号： G06F17/50 , G03F1/00
CPC分类号： G03F1/68
摘要： A method of adjusting the size of a photomask pattern is provided. First, the original coordinate is converted. Then the length and width of the original pattern are converted. Next, the size difference caused by the coordinate conversion is corrected according to the result of the length and width conversion.
摘要翻译：提供了调整光掩模图案尺寸的方法。首先，原始坐标被转换。然后转换原始图案的长度和宽度。接下来，根据长度和宽度转换的结果来校正由坐标转换引起的尺寸差异。

5. 发明授权

US06303455B1 Method for manufacturing capacitor 失效
标题翻译：制造电容器的方法
公开(公告)号：US06303455B1
公开(公告)日：2001-10-16
申请号：US09541450
申请日：2000-03-31
申请人： Chia-Hsin Hou , Tz-Guei Jung , Joe Ko
发明人： Chia-Hsin Hou , Tz-Guei Jung , Joe Ko
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L28/60
摘要： A method for manufacturing a capacitor is provided in the present invention. The bottom electrode of the capacitor is a polysilicon layer, and the top electrode of the capacitor is a silicide layer. Since depletion regions cannot be generated in the metal layer or the suicide layer, and the resistivity of the metal layer or the silicide layer is smaller than a conventional polysilicon layer, so that operating speed and frequency of the capacitor are both increased.
摘要翻译：本发明提供一种电容器的制造方法。电容器的底部电极是多晶硅层，电容器的顶部电极是硅化物层。由于在金属层或硅化物层中不能产生耗尽区，并且金属层或硅化物层的电阻率比常规多晶硅层小，所以电容器的工作速度和频率都增加。

6. 发明授权

US06309925B1 Method for manufacturing capacitor 失效
标题翻译：制造电容器的方法
公开(公告)号：US06309925B1
公开(公告)日：2001-10-30
申请号：US09643211
申请日：2000-08-22
申请人： Tz-Guei Jung , Chia-Hsin Hou , Joe Ko
发明人： Tz-Guei Jung , Chia-Hsin Hou , Joe Ko
IPC分类号： H01L218242
CPC分类号： H01L27/0629 , H01L28/40
摘要： A method for manufacturing a capacitor. A semiconductor substrate is divided into a peripheral circuit region and a memory cell region. An isolation structure is formed in the memory cell region. A gate oxide layer is formed over the substrate outside the isolation structure. A polysilicon layer is formed over the gate oxide layer and the isolation structure. The polysilicon layer and the gate oxide layer are patterned to form a bottom electrode above the isolation structure. In the meantime a polysilicon gate electrode is also formed above the peripheral circuit region. Spacers are formed on the sidewalls of the polysilicon gate electrode and the bottom electrode. A metal silicide layer is formed over the bottom electrode and the polysilicon gate electrode. A dielectric layer is formed over the metal silicide layer above the bottom electrode. A metallic layer is formed over the dielectric layer to form a capacitor.
摘要翻译：一种制造电容器的方法。半导体衬底被分成外围电路区域和存储单元区域。在存储单元区域中形成隔离结构。在隔离结构外部的衬底上形成栅氧化层。在栅极氧化物层和隔离结构上形成多晶硅层。图案化多晶硅层和栅极氧化物层以在隔离结构上方形成底部电极。同时，在外围电路区域上方也形成多晶硅栅电极。隔板形成在多晶硅栅电极和底电极的侧壁上。在底部电极和多晶硅栅电极上形成金属硅化物层。在底部电极上方的金属硅化物层上形成介电层。在电介质层上形成金属层以形成电容器。

7. 发明授权

US06271082B1 Method of fabricating a mixed circuit capacitor 有权
标题翻译：制造混合电路电容器的方法
公开(公告)号：US06271082B1
公开(公告)日：2001-08-07
申请号：US09557345
申请日：2000-04-25
申请人： Chia-Hsin Hou , Jyh-Kuang Lin , Tz-Guei Jung , Joe Ko
发明人： Chia-Hsin Hou , Jyh-Kuang Lin , Tz-Guei Jung , Joe Ko
IPC分类号： H01L218242
CPC分类号： H01L28/60 , H01L21/3212 , H01L21/76807 , H01L28/55
摘要： A method for fabricating a capacitor is applicable to a fabrication process for a mixed circuit. The method involves forming a first dielectric layer, a stop layer, and a second dielectric layer on a substrate having a conductive region. A first opening is then formed in the second dielectric layer, followed by forming a second opening in the stop layer and the first dielectric layer, so that the first opening and the second opening form a dual damascene opening for exposing the conductive region. The dual damascene opening is filled with a first conductive layer, so as to form a via plug and a lower electrode of the capacitor for connecting to the conductive region. A third dielectric layer, which is located between the lower electrode and a subsequent formed upper electrode, is then formed over the substrate, so that the lower electrode and a part of the second dielectric layer adjacent to the lower electrode are completely covered by the third dielectric layer. A patterned second conductive layer is formed on a part of the third dielectric layer, whereby an upper electrode for completely covering the lower electrode is formed.
摘要翻译：制造电容器的方法适用于混合电路的制造工艺。该方法包括在具有导电区域的基底上形成第一介电层，停止层和第二介质层。然后在第二电介质层中形成第一开口，随后在停止层和第一电介质层中形成第二开口，使得第一开口和第二开口形成用于暴露导电区域的双镶嵌开口。双镶嵌开口填充有第一导电层，以便形成用于连接到导电区域的电容器的通孔塞和下电极。然后在衬底上形成位于下电极和随后形成的上电极之间的第三电介质层，使得下电极和与下电极相邻的第二电介质层的一部分被第三电介质层完全覆盖电介质层。图案化的第二导电层形成在第三介电层的一部分上，由此形成用于完全覆盖下电极的上电极。

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