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1. 发明授权

US06280522B1 Quartz glass crucible for pulling silicon single crystal and production process for such crucible 有权
标题翻译：用于拉硅单晶的石英玻璃坩埚和这种坩埚的生产工艺
公开(公告)号：US06280522B1
公开(公告)日：2001-08-28
申请号：US09508695
申请日：2000-03-29
申请人： Hiroyuki Watanabe , Hiroyuki Miyazawa , Tatsuhiro Sato , Satoshi Soeta , Tetsuya Igarashi
发明人： Hiroyuki Watanabe , Hiroyuki Miyazawa , Tatsuhiro Sato , Satoshi Soeta , Tetsuya Igarashi
IPC分类号： C30B1322
CPC分类号： C03B19/095 , C03B2201/23 , C03B2201/24 , C30B15/10 , C30B35/002 , Y10S65/08
摘要： There is provided a quartz glass crucible for pulling a silicon single crystal and a production process for the crucible, wherein an inner surface of the crucible is crystallized without addition of impurities during pulling a silicon single crystal, thereby impurities serving as causes of crystal defects being not incorporated into the silicon single crystal, so that deterioration of its inner surface is suppressed to improve a crystallization ratio, and accordingly productivity of the quartz glass crucible as well as a quality of the silicon single crystal is improved, and the quartz glass crucible for pulling a silicon single crystal comprises a crucible base body (3) made of a translucent quartz glass layer and a synthetic quartz glass layer (4) formed on an inner wall surface of the crucible base body (3), wherein a portion encircled by a brown ring on an inner surface of the quartz glass crucible is uniformly crystallized during pulling the silicon single crystal.
摘要翻译：提供了一种用于拉制硅单晶的石英玻璃坩埚和用于坩埚的制造方法，其中在拉取硅单晶时坩埚的内表面结晶而不添加杂质，从而导致晶体缺陷的原因是不掺入到硅单晶中，从而抑制其内表面的劣化以提高结晶化率，从而提高了石英玻璃坩埚的生产率以及硅单晶的质量，并且提高了石英玻璃坩埚拉硅单晶包括由半透明石英玻璃层制成的坩埚基体（3）和形成在坩埚基体（3）的内壁表面上的合成石英玻璃层（4），其中包围由石英玻璃坩埚的内表面上的棕色环在拉制硅单晶时均匀结晶。

2. 发明授权

US5877027A Method for the analysis of impurity contents in silicon dioxide 失效
标题翻译：二氧化硅杂质含量分析方法
公开(公告)号：US5877027A
公开(公告)日：1999-03-02
申请号：US918133
申请日：1997-08-27
申请人： Katsuhiko Kemmochi , Kiyotaka Maekawa , Chuzaemon Tsuji , Manabu Saitou , Hiroyuki Miyazawa , Hiroyuki Watanabe
发明人： Katsuhiko Kemmochi , Kiyotaka Maekawa , Chuzaemon Tsuji , Manabu Saitou , Hiroyuki Miyazawa , Hiroyuki Watanabe
IPC分类号： G01N21/73 , G01N1/00 , G01N1/28 , G01N1/40 , G01N27/26 , G01N33/00 , G01N33/20
CPC分类号： G01N33/20 , G01N1/4044 , G01N2033/0095 , Y10T436/20 , Y10T436/25125
摘要： An analytical method for the quantitative determination of the impurities in silicon dioxide by which trace amounts of hardly soluble impurities contained in silicon dioxide can be reliably decomposed and converted into a solution so that the contents of all of the impurities contained in silicon dioxide or, in particular, zirconium in a natural quartz powder can be accurately determined. Silicon dioxide is decomposed with hydrofluoric acid or an acid mixture of hydrofluoric acid and another inorganic acid to give a decomposition solution which is, as such or after admixture with another inorganic acid, subjected to evaporation to dryness and the residue is heated to cause fusion with addition of a salt or hydroxide of an alkali metal followed by dissolution of the salt or hydroxide of an alkali metal with pure water or with an aqueous solution of an inorganic acid to give an aqueous solution which is subjected to quantitative analysis of the impurities therein.
摘要翻译：用于定量测定二氧化硅中的杂质的分析方法，其中二氧化硅中含有微量难溶的杂质可以被可靠地分解并转化成溶液，使得二氧化硅中所含的所有杂质的含量，特别地，可以精确地测定天然石英粉中的锆。二氧化硅用氢氟酸或氢氟酸与其他无机酸的酸性混合物分解，得到分解溶液，该分解溶液与其它无机酸混合后进行蒸发干燥，并将残余物加热至与加入碱金属的盐或氢氧化物，然后用纯水或无机酸的水溶液溶解碱金属的盐或氢氧化物，得到对其中的杂质进行定量分析的水溶液。

3. 发明授权

US5968259A High-purity quartz glass and method for the preparation thereof 失效
标题翻译：高纯石英玻璃及其制备方法
公开(公告)号：US5968259A
公开(公告)日：1999-10-19
申请号：US917933
申请日：1997-08-27
申请人： Katsuhiko Kemmochi , Hiroyuki Miyazawa , Hiroyuki Watanabe , Kiyotaka Maekawa , Chuzaemon Tsuji , Manabu Saitou
发明人： Katsuhiko Kemmochi , Hiroyuki Miyazawa , Hiroyuki Watanabe , Kiyotaka Maekawa , Chuzaemon Tsuji , Manabu Saitou
IPC分类号： C03C1/00 , C03C3/06 , C30B15/10 , C30B35/00 , C30B29/18
CPC分类号： C03C3/06 , C03C1/006 , C30B15/10 , C30B35/002 , C03C2201/02 , C03C2203/10 , Y10T29/40
摘要： Provided are high-purity quartz glass having a high purity, in particular, with little zirconium (Zr) and manufactured at low costs from natural quartz as the starting material and a method for the preparation thereof. High-purity quartz glass is manufactured, in a method for the preparation of natural quartz glass which is prepared by subjecting crystalline natural quartz to fusion by heating, in conducting refining of the starting material of the crystalline natural quartz by successively practicing a combination of at least one unit refining procedure, in a procedure in which a portion of the starting quartz after practicing the specified unit refining procedure is taken by sampling for analysis, the same is decomposed with hydrofluoric acid or an acid mixture of hydrofluoric acid and another inorganic acid, the decomposition solution is subjected to evaporation to dryness either as such or after addition of another inorganic acid, the residue is melted by heating with admixture of a salt or hydroxide of an alkali metal, the salt or hydroxide of the alkali metal is then dissolved in an aqueous solution of an inorganic acid or in pure water, the solution is subjected to quantitative analysis for the impurities therein to determine the contents of impurities in the crystalline natural quartz and the refined crystalline natural quartz, of which the content of impurities has been found to be lower than a specified value, is subjected to fusion by heating as a starting material to prepare high-purity quartz glass.
摘要翻译：提供了具有高纯度的高纯度石英玻璃，特别是少量锆（Zr），并以天然石英作为起始原料以低成本制造，以及其制备方法。制造高纯度石英玻璃的方法中，天然石英玻璃的制备方法是将结晶天然石英通过加热进行熔融制备，在通过连续地实施在至少一个单元精制程序，在通过取样进行分析之后，通过取样进行一部分实施了规定的单元精炼处理后的起始石英的一部分，同时用氢氟酸或氢氟酸与其它无机酸的酸混合物分解，将分解溶液按照本身或加入另一种无机酸进行蒸发干燥后，通过用碱金属的盐或氢氧化物的混合物加热将残余物熔化，然后将碱金属的盐或氢氧化物溶于无机酸的水溶液或纯水中，对该溶液进行定量分析 e杂质以确定结晶天然石英中的杂质含量和发现杂质含量低于规定值的精制结晶天然石英通过加热作为原料进行熔融以制备高纯石英玻璃。

4. 发明授权

US06511365B2 Lapping machine 失效
标题翻译：研磨机
公开(公告)号：US06511365B2
公开(公告)日：2003-01-28
申请号：US09459036
申请日：1999-12-10
申请人： Shigeo Terashima , Hiroyuki Miyazawa
发明人： Shigeo Terashima , Hiroyuki Miyazawa
IPC分类号： B24B100
CPC分类号： B24B53/017 , B24B37/048 , B24B49/14 , G11B5/1871 , G11B5/3116 , G11B5/3163 , G11B5/3903
摘要： An object of the present invention is to provide a lapping machine in which abrasive grains can be efficiently and completely removed from a lapping plate. In the lapping machine of the present invention, a lapping plate has a lapping face and rotates about a rotary shaft. A moving member has a wiping face extended in a longitudinal and moves, in a plane parallel to the lapping face of the lapping plate, in the direction perpendicular to the wiping face. A driving mechanism moves the moving member. With this structure, the moving member securely catches and removes foreign substances from the lapping plate. The foreign substances left can be completely removed in a short time and the working efficiency of the lapping steps can be highly improved.
摘要翻译：本发明的目的是提供一种研磨机，其中磨粒可以从研磨盘中有效地和完全地除去。在本发明的研磨机中，研磨板具有研磨面并围绕旋转轴旋转。移动构件具有沿纵向延伸的擦拭面，在与研磨板的研磨面平行的平面中，在与擦拭面垂直的方向上移动。驱动机构移动移动构件。利用这种结构，移动构件牢固地捕获并从研磨板上去除异物。留下的异物可以在短时间内完全去除，研磨步骤的工作效率可以大大提高。

5. 发明授权

US5640282A Base body of reflecting mirror and method for preparing the same 失效
标题翻译：反射镜的基体及其制备方法
公开(公告)号：US5640282A
公开(公告)日：1997-06-17
申请号：US775095
申请日：1991-10-11
申请人： Yoshiaki Ise , Hiroyuki Miyazawa , Hiroyuki Kimura , Shinichi Okoshi , Tatsumasa Nakamura , Toshiyuki Kato
发明人： Yoshiaki Ise , Hiroyuki Miyazawa , Hiroyuki Kimura , Shinichi Okoshi , Tatsumasa Nakamura , Toshiyuki Kato
IPC分类号： G02B5/08 , G02B5/10 , G02B7/182 , G02B7/183
CPC分类号： G02B7/183 , G02B5/08 , G02B5/10 , Y10S359/90 , Y10T428/249969 , Y10T428/249976 , Y10T428/249977
摘要： A light-weight base body of a reflecting mirror, such as those used in reflecting astronomical telescopes, is proposed which is made from fused silica glass or high-silica glass and is advantageous in respect of the excellent thermal and mechanical stability in dimensions to ensure high performance of the reflecting mirror. The base body is composed of a front plate, i.e. a surface plate to provide the optical surface, and a supporting body of porous foamed glass integrally bonded to the front plate. These two parts of the base body can be bonded together by sandwiching a layer of a finely divided silica powder therebetween and heating the assemblage at a temperature higher than the softening point of the silica powder so that the silica powder is softened or melted to firmly join the two parts sandwiching the powder layer. The base body can be further improved in respect of the mechanical stability by providing a rear plate backing the porous foamed body and a reinforcing hoop-like side layer surrounding the side surface of the porous foamed body, each made from fused quartz glass or high-silica glass and bonded to the porous foamed body by utilizing melting of a layer of silica powder therebetween.
摘要翻译：提出了一种反射镜的轻质基体，例如用于反射天文望远镜的反射镜，其由熔融石英玻璃或高硅石玻璃制成，并且在尺寸方面优良的热和机械稳定性是有利的，以确保高性能的反光镜。基体由前板，即提供光学表面的表面板和与前板一体地结合的多孔泡沫玻璃的支撑体组成。基体的这两个部分可以通过在其间夹有细碎的二氧化硅粉末层而将它们粘合在一起，并在高于二氧化硅粉末的软化点的温度下加热组合物，使得二氧化硅粉末软化或熔化以牢固地连接两部分夹在粉末层上。通过提供背面多孔泡沫体的后板和围绕多孔泡沫体的侧表面的加强箍型侧层，每个由熔融石英玻璃或高熔点石英玻璃制成，可以进一步改善基体的机械稳定性，二氧化硅玻璃，并通过利用二氧化硅粉末之间的熔融而与多孔发泡体结合。

6. 发明授权

US4962052A Method for producing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US4962052A
公开(公告)日：1990-10-09
申请号：US478050
申请日：1990-02-07
申请人： Kyoichiro Asayama , Hiroyuki Miyazawa , Yutaka Kobayashi , Seigou Yukutake
发明人： Kyoichiro Asayama , Hiroyuki Miyazawa , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L27/105 , H01L29/10 , H01L29/73 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L27/105
摘要： A method for producing a memory LSI having in its peripheral circuitry an MISFET of LDD structure and a vertical type bipolar transistor is disclosed. More particularly, an impurity for forming a low impurity concentration region of the said MISFET of LDD structure is introduced sideways of an emitter-base junction of the bipolar transistor. By the introduction of the said impurity, an effective impurity concentration near the base surface is reduced and the cut-off frequency of the bipolar transistor is improved.
摘要翻译：公开了一种在其外围电路中具有LDD结构的MISFET和垂直型双极晶体管的存储器LSI的制造方法。更具体地，用于形成LDD结构的所述MISFET的低杂质浓度区域的杂质被侧向引入双极晶体管的发射极 - 基极结。通过引入所述杂质，降低了基极表面附近的有效杂质浓度，提高了双极晶体管的截止频率。

7. 发明授权

US6043118A Semiconductor memory circuit device and method for fabricating a semiconductor memory device circuit 失效
标题翻译：半导体存储器电路器件及半导体存储器件电路的制造方法
公开(公告)号：US6043118A
公开(公告)日：2000-03-28
申请号：US800018
申请日：1997-02-13
申请人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
发明人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/10808
摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.
摘要翻译：在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。

8. 发明授权

US5389558A Method of making a semiconductor memory circuit device 失效
标题翻译：制造半导体存储器电路器件的方法
公开(公告)号：US5389558A
公开(公告)日：1995-02-14
申请号：US104014
申请日：1993-08-10
申请人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
发明人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/10808
摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.
摘要翻译：在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。

9. 发明授权

US5268587A Semiconductor integrated circuit device including a dielectric breakdown prevention circuit 失效
标题翻译：包括绝缘击穿防止电路的半导体集成电路装置
公开(公告)号：US5268587A
公开(公告)日：1993-12-07
申请号：US786750
申请日：1991-11-01
申请人： Jun Murata , Hideyuki Miyazawa , Kyoichiro Asayama , Akihiro Tamba , Seigou Yukutake , Hiroyuki Miyazawa , Yutaka Kobayashi , Tomoyuki Someya
发明人： Jun Murata , Hideyuki Miyazawa , Kyoichiro Asayama , Akihiro Tamba , Seigou Yukutake , Hiroyuki Miyazawa , Yutaka Kobayashi , Tomoyuki Someya
IPC分类号： H01L27/105 , H01L27/108 , H01L29/06 , H01L29/78
CPC分类号： H01L27/10805 , H01L27/105
摘要： A semiconductor integrated circuit device includes a dielectric breakdown prevention circuit coupled to an external terminal for protecting an input stage circuit. The prevention circuit has bipolar transistors and complementary MISFETs including a first MISFET of a first conductivity type and a second MISFET of a second conductivity type. A first semiconductor region of the first conductivity type is formed by the same layer as a well region in which the second MISFET is formed. A second semiconductor region of the second conductivity type is formed in said first semiconductor region by the same layer as source and drain regions of the second MISFET. These first and second semiconductor regions form a first PN junction diode. The external terminal is electrically coupled to one end portion of said second semiconductor region. A high impurity conductivity type buried third semiconductor region underlies the said second semiconductor region, and is formed by the same layer as a region isolating the bipolar transistors. This third region is disposed at the bottom surface of said first semiconductor region. A fourth semiconductor region of the second conductivity type is also formed in said first semiconductor region by the same layer used for collector contact regions of the bipolar transistors, and is connected with another end portion of said second semiconductor region, in contact with the third semiconductor region. The fourth semiconductor region is coupled to the input stage circuit, and the third and fourth semiconductor regions form a second PN junction diode.
摘要翻译：半导体集成电路器件包括耦合到外部端子的绝缘击穿防止电路，用于保护输入级电路。防止电路具有双极晶体管和互补MISFET，其包括第一导电类型的第一MISFET和第二导电类型的第二MISFET。第一导电类型的第一半导体区域由与其中形成第二MISFET的阱区相同的层形成。第二导电类型的第二半导体区域通过与第二MISFET的源极和漏极区域相同的层在所述第一半导体区域中形成。这些第一和第二半导体区域形成第一PN结二极管。外部端子电耦合到所述第二半导体区域的一个端部。高杂质导电型掩埋的第三半导体区域位于所述第二半导体区域的下方，并且由与隔离双极晶体管的区域相同的层形成。该第三区域设置在所述第一半导体区域的底表面。第二导电类型的第四半导体区域也通过与用于双极晶体管的集电极接触区域的相同的层形成在所述第一半导体区域中，并且与所述第二半导体区域的与第三半导体接触的另一个端部连接地区。第四半导体区域耦合到输入级电路，并且第三和第四半导体区域形成第二PN结二极管。

10. 发明授权

US5917211A Semiconductor integrated circuit, method of fabricating the same and apparatus for fabricating the same 失效
标题翻译：半导体集成电路及其制造方法及其制造装置
公开(公告)号：US5917211A
公开(公告)日：1999-06-29
申请号：US979543
申请日：1997-11-25
申请人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
发明人： Jun Murata , Yoshitaka Tadaki , Hiroko Kaneko , Toshihiro Sekiguchi , Hiroyuki Uchiyama , Hisashi Nakamura , Toshio Maeda , Osamu Kasahara , Hiromichi Enami , Atsushi Ogishima , Masaki Nagao , Michimasa Funabashi , Yasuo Kiguchi , Masayuki Kojima , Atsuyoshi Koike , Hiroyuki Miyazawa , Masato Sadaoka , Kazuya Kadota , Tadashi Chikahara , Kazuo Nojiri , Yutaka Kobayashi
IPC分类号： H01L21/8234 , H01L27/105 , H01L27/08 , H01L29/76 , H01L29/94
CPC分类号： H01L27/105 , H01L21/823425
摘要： A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.
摘要翻译：一种半导体集成电路，包括构成存储系统的存储单元的第一n沟道MISFET，构成存储系统的外围电路的第二n沟道MISFET和构成外围电路中的输出电路的第三n沟道MISFET。当这些MISFET的各个栅极长度基本相同时，第一n沟道MISFET，第二n沟道MISFET和第三n沟道MISFET的阈值电压依次减小。

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