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1. 发明授权

US5237187A Semiconductor memory circuit device and method for fabricating same 失效
标题翻译：半导体存储器电路器件及其制造方法
公开(公告)号：US5237187A
公开(公告)日：1993-08-17
申请号：US799541
申请日：1991-11-27
申请人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
发明人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/10808
摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region, which is a memory cell array region, a first MISFET having a gate electrode and source and drain regions; first and second capacitor electrodes and a dielectric film extended over a first insulating film and over the gate electrode; a second insulating film disposed on the second capacitor electrode; a third insulating film interposed between the first insulating film and first capacitor electrode; and a first wiring positioned on the second insulating film. In a second region of the device, which is a peripheral circuit region, there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a second insulating film on a third insulating film, the third insulating film being interposed between the first and second insulating films; and a second wiring on the second insulating film. The second wiring is formed by the same level conductor layer as that forming the first wiring. Similarly, the first through third insulating films of the first region are correspondingly associated with the first through third insulating films of the second region, respectively.
摘要翻译：在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，存在作为存储单元阵列区域的第一区域，第一 MISFET具有栅极电极和源极和漏极区域; 第一和第二电容器电极以及在第一绝缘膜上并在栅电极上方延伸的电介质膜; 设置在所述第二电容器电极上的第二绝缘膜; 介于所述第一绝缘膜和所述第一电容器电极之间的第三绝缘膜; 以及位于第二绝缘膜上的第一布线。在作为外围电路区域的器件的第二区域中，存在具有栅极电极和源极和漏极区域的第二MISFET，栅电极上的第一绝缘膜; 在第三绝缘膜上的第二绝缘膜，所述第三绝缘膜介于所述第一和第二绝缘膜之间; 以及在第二绝缘膜上的第二布线。第二布线由与形成第一布线的层相同的导体层形成。类似地，第一区域的第一至第三绝缘膜分别与第二区域的第一至第三绝缘膜相关联。

2. 发明授权

US5631182A Method of making a semiconductor memory circuit device 失效
标题翻译：制造半导体存储器电路器件的方法
公开(公告)号：US5631182A
公开(公告)日：1997-05-20
申请号：US327861
申请日：1994-10-18
申请人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
发明人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/10808
摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.
摘要翻译：在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。

3. 发明授权

US6043118A Semiconductor memory circuit device and method for fabricating a semiconductor memory device circuit 失效
标题翻译：半导体存储器电路器件及半导体存储器件电路的制造方法
公开(公告)号：US6043118A
公开(公告)日：2000-03-28
申请号：US800018
申请日：1997-02-13
申请人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
发明人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/10808
摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.
摘要翻译：在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。

4. 发明授权

US5389558A Method of making a semiconductor memory circuit device 失效
标题翻译：制造半导体存储器电路器件的方法
公开(公告)号：US5389558A
公开(公告)日：1995-02-14
申请号：US104014
申请日：1993-08-10
申请人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
发明人： Naokatsu Suwanai , Hiroyuki Miyazawa , Atushi Ogishima , Masaki Nagao , Kyoichiro Asayama , Hiroyuki Uchiyama , Yoshiyuki Kaneko , Takashi Yoneoka , Kozo Watanabe , Kazuya Endo , Hiroki Soeda
IPC分类号： H01L21/8242 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10844 , H01L27/10805 , H01L27/10808
摘要： In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region as a memory cell array region a first MISFET having a gate electrode and source and drain regions; first and second capacity electrodes and a dielectric film extending onto a first insulating film on the gate electrode; a second insulating film positioned on the second capacity electrode; and a first wiring positioned on the second insulating film, while in a second region as a peripheral circuit region there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a third insulating film on the first insulating film; a second insulating film on the third insulating film; and a second wiring on the second insulating film.
摘要翻译：在其中每个存储单元由存储单元选择MISFET的串联电路和层叠结构的信息存储电容器构成的半导体存储器电路器件中，在第一区域中存在作为存储单元阵列区域的第一MISFET，其具有栅极电极和源极和漏极区域; 第一和第二电容电极和延伸到栅电极上的第一绝缘膜上的电介质膜; 位于所述第二容量电极上的第二绝缘膜; 以及位于所述第二绝缘膜上的第一布线，而在作为外围电路区域的第二区域中存在具有栅极电极和源极和漏极区域的第二MISFET; 栅电极上的第一绝缘膜; 第一绝缘膜上的第三绝缘膜; 第三绝缘膜上的第二绝缘膜; 以及在第二绝缘膜上的第二布线。

5. 发明授权

US4962052A Method for producing semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件的制造方法
公开(公告)号：US4962052A
公开(公告)日：1990-10-09
申请号：US478050
申请日：1990-02-07
申请人： Kyoichiro Asayama , Hiroyuki Miyazawa , Yutaka Kobayashi , Seigou Yukutake
发明人： Kyoichiro Asayama , Hiroyuki Miyazawa , Yutaka Kobayashi , Seigou Yukutake
IPC分类号： H01L21/331 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L27/105 , H01L29/10 , H01L29/73 , H01L29/732
CPC分类号： H01L29/66272 , H01L21/8249 , H01L27/0623 , H01L29/1004 , H01L27/105
摘要： A method for producing a memory LSI having in its peripheral circuitry an MISFET of LDD structure and a vertical type bipolar transistor is disclosed. More particularly, an impurity for forming a low impurity concentration region of the said MISFET of LDD structure is introduced sideways of an emitter-base junction of the bipolar transistor. By the introduction of the said impurity, an effective impurity concentration near the base surface is reduced and the cut-off frequency of the bipolar transistor is improved.
摘要翻译：公开了一种在其外围电路中具有LDD结构的MISFET和垂直型双极晶体管的存储器LSI的制造方法。更具体地，用于形成LDD结构的所述MISFET的低杂质浓度区域的杂质被侧向引入双极晶体管的发射极 - 基极结。通过引入所述杂质，降低了基极表面附近的有效杂质浓度，提高了双极晶体管的截止频率。

6. 发明授权

US5268587A Semiconductor integrated circuit device including a dielectric breakdown prevention circuit 失效
标题翻译：包括绝缘击穿防止电路的半导体集成电路装置
公开(公告)号：US5268587A
公开(公告)日：1993-12-07
申请号：US786750
申请日：1991-11-01
申请人： Jun Murata , Hideyuki Miyazawa , Kyoichiro Asayama , Akihiro Tamba , Seigou Yukutake , Hiroyuki Miyazawa , Yutaka Kobayashi , Tomoyuki Someya
发明人： Jun Murata , Hideyuki Miyazawa , Kyoichiro Asayama , Akihiro Tamba , Seigou Yukutake , Hiroyuki Miyazawa , Yutaka Kobayashi , Tomoyuki Someya
IPC分类号： H01L27/105 , H01L27/108 , H01L29/06 , H01L29/78
CPC分类号： H01L27/10805 , H01L27/105
摘要： A semiconductor integrated circuit device includes a dielectric breakdown prevention circuit coupled to an external terminal for protecting an input stage circuit. The prevention circuit has bipolar transistors and complementary MISFETs including a first MISFET of a first conductivity type and a second MISFET of a second conductivity type. A first semiconductor region of the first conductivity type is formed by the same layer as a well region in which the second MISFET is formed. A second semiconductor region of the second conductivity type is formed in said first semiconductor region by the same layer as source and drain regions of the second MISFET. These first and second semiconductor regions form a first PN junction diode. The external terminal is electrically coupled to one end portion of said second semiconductor region. A high impurity conductivity type buried third semiconductor region underlies the said second semiconductor region, and is formed by the same layer as a region isolating the bipolar transistors. This third region is disposed at the bottom surface of said first semiconductor region. A fourth semiconductor region of the second conductivity type is also formed in said first semiconductor region by the same layer used for collector contact regions of the bipolar transistors, and is connected with another end portion of said second semiconductor region, in contact with the third semiconductor region. The fourth semiconductor region is coupled to the input stage circuit, and the third and fourth semiconductor regions form a second PN junction diode.
摘要翻译：半导体集成电路器件包括耦合到外部端子的绝缘击穿防止电路，用于保护输入级电路。防止电路具有双极晶体管和互补MISFET，其包括第一导电类型的第一MISFET和第二导电类型的第二MISFET。第一导电类型的第一半导体区域由与其中形成第二MISFET的阱区相同的层形成。第二导电类型的第二半导体区域通过与第二MISFET的源极和漏极区域相同的层在所述第一半导体区域中形成。这些第一和第二半导体区域形成第一PN结二极管。外部端子电耦合到所述第二半导体区域的一个端部。高杂质导电型掩埋的第三半导体区域位于所述第二半导体区域的下方，并且由与隔离双极晶体管的区域相同的层形成。该第三区域设置在所述第一半导体区域的底表面。第二导电类型的第四半导体区域也通过与用于双极晶体管的集电极接触区域的相同的层形成在所述第一半导体区域中，并且与所述第二半导体区域的与第三半导体接触的另一个端部连接地区。第四半导体区域耦合到输入级电路，并且第三和第四半导体区域形成第二PN结二极管。

7. 发明授权

US5081515A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5081515A
公开(公告)日：1992-01-14
申请号：US496328
申请日：1990-03-20
申请人： Jun Murata , Hideyuki Miyazawa , Kyoichiro Asayama , Akihiro Tamba , Seigou Yukutake , Hiroyuki Miyazawa , Yutaka Kobayashi , Tomoyuki Someya
发明人： Jun Murata , Hideyuki Miyazawa , Kyoichiro Asayama , Akihiro Tamba , Seigou Yukutake , Hiroyuki Miyazawa , Yutaka Kobayashi , Tomoyuki Someya
IPC分类号： H01L29/73 , H01L21/331 , H01L21/8222 , H01L21/8242 , H01L21/8248 , H01L21/8249 , H01L27/06 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/732
CPC分类号： H01L27/10805 , H01L27/105
摘要： A semiconductor integrated circuit device is equipped with a DRAM whose memory cell is formed as a series circuit of a memory cell selection MISFET and a data storage capacitance element of a stacked structure. A complementary data line extends on an upper electrode layer of the data storage capacitance element of the stacked structure through an inter-level insulation film which is connected to a semiconductor region of the memory cell selection MISFET. To reduce parasitic capacitance the wiring width of the complementary data line is formed to be smaller than the film thickness of the inter-level insulation film between the complementary data line and the upper electrode layer of said data storage capacitance element of the stacked structure.
摘要翻译：半导体集成电路器件配备有DRAM，其存储单元形成为存储单元选择MISFET和层叠结构的数据存储电容元件的串联电路。互补数据线通过连接到存储单元选择MISFET的半导体区域的层间绝缘膜在层叠结构的数据存储电容元件的上电极层上延伸。为了减小寄生电容，互补数据线的布线宽度形成为小于互补数据线与层叠结构的数据存储电容元件的上电极层之间的层间绝缘膜的膜厚度。

8. 发明授权

US5045904A Semiconductor device including an improved trench arrangement 失效
标题翻译：包括改进的沟槽布置的半导体器件
公开(公告)号：US5045904A
公开(公告)日：1991-09-03
申请号：US286870
申请日：1988-12-20
申请人： Yutaka Kobayashi , Akihiro Tanba , Ryoichi Hori , Kyoichiro Asayama , Seigoh Yukutake , Hiroyuki Miyazawa , Kazumasa Yanagisawa , Goro Kitsukawa
发明人： Yutaka Kobayashi , Akihiro Tanba , Ryoichi Hori , Kyoichiro Asayama , Seigoh Yukutake , Hiroyuki Miyazawa , Kazumasa Yanagisawa , Goro Kitsukawa
IPC分类号： H01L27/10 , H01L21/8242 , H01L21/8249 , H01L27/06 , H01L27/108 , H01L29/94
CPC分类号： H01L29/945 , H01L27/10829
摘要： A small and reliable semiconductor device is provided in a substrate which has an isolation trench and a capacitor trench. The isolation trench isolates a bipolar transistor from other semiconductor devices, and the capacitor trench provides capacitance to a memory cell which is formed in the substrate. The interior of the device isolation trench is kept in a floating state with respect to the surrounding semiconductor regions by forming an insulating film over the inner surface of the trench. In the capacitor trench, insulating layers and resilient conductive layers are formed alternately to form capacitance between the opposing conductive layers.
摘要翻译：在具有隔离沟槽和电容器沟槽的衬底中提供小型且可靠的半导体器件。隔离沟槽将双极晶体管与其它半导体器件隔离，并且电容器沟槽为在衬底中形成的存储器单元提供电容。器件隔离沟槽的内部通过在沟槽的内表面上形成绝缘膜而相对于周围的半导体区域保持浮置状态。在电容器沟槽中，交替地形成绝缘层和弹性导电层，以在相对的导电层之间形成电容。

9. 发明授权

US06512245B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06512245B2
公开(公告)日：2003-01-28
申请号：US09859045
申请日：2001-05-17
申请人： Shuji Ikeda , Satoshi Meguro , Kyoichiro Asayama , Eri Fujita , Koichiro Ishibashi , Toshiro Aoto , Sadayuki Morita , Atsuyoshi Koike , Masayuki Kojima , Yasuo Kiguchi , Kazuyuki Suko , Fumiyuki Kanai , Naotaka Hashimoto , Toshiaki Yamanaka
发明人： Shuji Ikeda , Satoshi Meguro , Kyoichiro Asayama , Eri Fujita , Koichiro Ishibashi , Toshiro Aoto , Sadayuki Morita , Atsuyoshi Koike , Masayuki Kojima , Yasuo Kiguchi , Kazuyuki Suko , Fumiyuki Kanai , Naotaka Hashimoto , Toshiaki Yamanaka
IPC分类号： H01L2972
CPC分类号： H01L27/11 , H01L27/1104 , Y10S257/903 , Y10S257/904
摘要： A static random access memory comprising memory cells each composed of transfer MISFETs controlled by word lines and of a flip-flop circuit made of driver MISFETs and load MISFETs. The top of the load MISFETs is covered with supply voltage lines so that capacitor elements of a stacked structure are formed between the gate electrodes of the load MISFETs and the supply voltage lines.
摘要翻译：一种静态随机存取存储器，包括由字线控制的转移MISFET和由驱动器MISFET和负载MISFET构成的触发电路组成的存储单元。负载MISFET的顶部覆盖有电源电压线，使得层叠结构的电容器元件形成在负载MISFET的栅电极和电源电压线之间。

10. 发明授权

US06881597B2 Method of manufacturing a semiconductor device to provide a plurality of test element groups (TEGs) in a scribe region 失效
标题翻译：制造半导体器件以在划线区域中提供多个测试元件组（TEG）的方法
公开(公告)号：US06881597B2
公开(公告)日：2005-04-19
申请号：US10051056
申请日：2002-01-22
申请人： Kyoichiro Asayama , Yasuhiro Mitsui , Fumiko Arakawa , Shiro Kamohara , Yuzuru Ohji
发明人： Kyoichiro Asayama , Yasuhiro Mitsui , Fumiko Arakawa , Shiro Kamohara , Yuzuru Ohji
IPC分类号： G01R31/28 , H01L21/28 , H01L21/3205 , H01L21/66 , H01L21/822 , H01L23/52 , H01L23/544 , H01L27/04 , H01L21/00
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed is a technique capable of improving a yield of a semiconductor device by measuring a plurality of TEGs arranged in a scribe region. A first electrode pad connected to each terminal of a TEG is formed as a rectangular, minute, isolated pattern having a side length of about 0.5 μm or shorter and constituted of an uppermost layer wiring on a semiconductor substrate, and therefore, a great number of TEGs can be laid in a first scribe region. The characteristic evaluation or the failure analysis is performed by contacting a nanoprobe having a tip radius of curvature of 0.05 μm to 0.8 μm to the first electrode pad.
摘要翻译：公开了一种能够通过测量布置在划线区域中的多个TEG来提高半导体器件的产量的技术。连接到TEG的每个端子的第一电极焊盘形成为具有约0.5μm或更短的侧边长度并由半导体衬底上的最上层布线构成的矩形，微小隔离图案，因此，大量 TEG可以放在第一个划痕区域。特征评估或故障分析是通过将具有0.05μm至0.8μm的尖端曲率半径的纳米探针接触到第一电极焊盘来进行的。

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