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1. 发明申请

US20100132888A1 Plasma Processing Apparatus 审中-公开
标题翻译：等离子体处理装置
公开(公告)号：US20100132888A1
公开(公告)日：2010-06-03
申请号：US12699382
申请日：2010-02-03
申请人： Shoji IKUHARA , Daisuke Shiraishi , Hideyuki Yamamoto , Akira Kagoshima , Hiromichi Enami , Yosuke Karashima , Eiji Matsumoto
发明人： Shoji IKUHARA , Daisuke Shiraishi , Hideyuki Yamamoto , Akira Kagoshima , Hiromichi Enami , Yosuke Karashima , Eiji Matsumoto
IPC分类号： H01L21/306
CPC分类号： H01L21/67069 , H01J37/32935 , H01L21/67253
摘要： A plasma processing apparatus includes a plasma processing main frame, and an apparatus controller controlling the plasma processing main frame. The plasma processing main frame has a vacuum process chamber, an exhaust device, a mass flow controller, a stage electrode receiving a workpiece, a high-frequency electrical source to, and a transfer device placing the workpiece on the stage electrode and carrying out the processed workpiece. The apparatus controller controls the plasma processing main frame in accordance with a predetermined procedure and is provided with a diagnosis device which acquires a plurality of recipes for processing workpieces carried in the chamber and apparatus parameters of the plasma processing apparatus when a specific recipe of the above recipes is executed, whereby the condition of the plasma processing main frame is diagnosed based on the acquired apparatus parameters.
摘要翻译：等离子体处理装置包括等离子体处理主框架和控制等离子体处理主框架的装置控制器。等离子体处理主框架具有真空处理室，排气装置，质量流量控制器，接收工件的阶段电极，高频电源和将工件放置在平台电极上的传送装置，加工工件。设备控制器按照预定的步骤控制等离子体处理主框架，并且设置有诊断装置，该诊断装置获取用于处理在室中携带的工件的多个配方和等离子体处理装置的装置参数，当上述特定配方执行配方，由此基于所获取的装置参数来诊断等离子体处理主框架的状态。

2. 发明申请

US20080011422A1 Plasma Processing System And Apparatus And A Sample Processing Method 有权
标题翻译：等离子体处理系统及装置及样品处理方法
公开(公告)号：US20080011422A1
公开(公告)日：2008-01-17
申请号：US11780014
申请日：2007-07-19
申请人： Toshio MASUDA , Tatehito USUI , Mitsuru SUEHIRO , Hiroshi KANEKIYO , Hideyuki YAMAMOTO , Kazue TAKAHASHI , Hiromichi ENAMI
发明人： Toshio MASUDA , Tatehito USUI , Mitsuru SUEHIRO , Hiroshi KANEKIYO , Hideyuki YAMAMOTO , Kazue TAKAHASHI , Hiromichi ENAMI
IPC分类号： H05H1/00
CPC分类号： H01L21/67069 , G01N21/68 , H01J37/32082 , H01J37/32935 , H01J37/32972
摘要： A plasma processing apparatus includes a vacuum vessel with a sample stage having a mounting surface disposed in a process chamber, and a plate having substantially uniform thickness and electric power applied thereto constituting a ceiling of the chamber. The plate is disposed opposite to and substantially parallel with the sample stage so as to cover the whole area of the stage mounting surface and has a through-hole therein. An optical transmitter with a diameter larger than a diameter of the though-hole is disposed inside of the vacuum vessel and has an end face at a position above and spaced a small distance a back surface of the plate so as to receive light from the chamber via the through-hole. The optical transmitter is independently detachable with respect to the back surface of the plate.
摘要翻译：等离子体处理装置包括具有设置在处理室中的安装表面的样品台的真空容器，以及构成室的天花板的基本均匀的厚度和电功率的板。该板与样品台相对设置并基本上平行，以覆盖舞台安装表面的整个区域并且在其中具有通孔。直径大于通孔直径的光发射器设置在真空容器的内部，并且具有位于板的后表面上方且间隔很小距离的位置处的端面，以便接收来自腔室的光通过通孔。光发射器相对于板的后表面独立地可拆卸。

3. 发明授权

US07169254B2 Plasma processing system and apparatus and a sample processing method 有权
标题翻译：等离子体处理系统和设备及样品处理方法
公开(公告)号：US07169254B2
公开(公告)日：2007-01-30
申请号：US10732285
申请日：2003-12-11
申请人： Toshio Masuda , Tatehito Usui , Mitsuru Suehiro , Hiroshi Kanekiyo , Hideyuki Yamamoto , Kazue Takahashi , Hiromichi Enami
发明人： Toshio Masuda , Tatehito Usui , Mitsuru Suehiro , Hiroshi Kanekiyo , Hideyuki Yamamoto , Kazue Takahashi , Hiromichi Enami
IPC分类号： H01L21/00 , C23C16/00 , C23C14/00
CPC分类号： H01L21/67069 , G01N21/68 , H01J37/32082 , H01J37/32935 , H01J37/32972
摘要： A plasma processing apparatus having a sample stage disposed inside a vacuum chamber and a plate member disposed opposing to a sample which is placed on the sample stage and supplied with electric power. The sample is processed using a plasma generated between the sample stage and the plate member and a measuring port is disposed at a back side of the plate member. The measuring port includes an optical transmitter which receives light from a surface of the sample, and a seal which vacuum-seals between an atmospheric side and vacuum side of the vacuum chamber.
摘要翻译：一种等离子体处理装置，其具有设置在真空室内的样品台和与放置在样品台上并提供电力的样品相对设置的板构件。使用在样品台和板构件之间产生的等离子体处理样品，并且测量端口设置在板构件的后侧。测量端口包括从样品表面接收光的光发射器，以及在真空室的大气侧和真空侧之间进行真空密封的密封件。

4. 发明授权

US5811316A Method of forming teos oxide and silicon nitride passivation layer on aluminum wiring 失效
标题翻译：在铝线上形成氧化硅和氮化硅钝化层的方法
公开(公告)号：US5811316A
公开(公告)日：1998-09-22
申请号：US460931
申请日：1995-06-05
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L21/28
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

5. 发明授权

US5646489A Plasma generator with mode restricting means 失效
标题翻译：具有模式限制装置的等离子发生器
公开(公告)号：US5646489A
公开(公告)日：1997-07-08
申请号：US432861
申请日：1995-05-02
申请人： Yutaka Kakehi , Yoshinao Kawasaki , Keizo Suzuki , Kazuo Nojiri , Hiromichi Enami , Tetsunori Kaji , Seiichi Watanabe , Yoshifumi Ogawa
发明人： Yutaka Kakehi , Yoshinao Kawasaki , Keizo Suzuki , Kazuo Nojiri , Hiromichi Enami , Tetsunori Kaji , Seiichi Watanabe , Yoshifumi Ogawa
IPC分类号： C23C16/511 , H01J37/32 , H05H1/46
CPC分类号： H01J37/32229 , C23C16/511 , H01J37/32192 , H01J37/32266 , H01J37/32284
摘要： A plasma processing apparatus has a waveguide along which microwaves are propagated from a microwave generator to a plasma-forming region in a low-pressure processing chamber. The waveguide has a large cross-sectional area, to enable a large region of plasma to be achieved. Uniformity and stability of the plasma are improved by a mode restrictor which inhibits mixing of propagation modes which is otherwise liable to occur in a wide waveguide. The mode restrictor consists of electrically conductive dividers which divide the waveguide cross-section into an array of sub-guides before the plasma-forming region.
摘要翻译：等离子体处理装置具有微波从微波发生器传播到低压处理室中的等离子体形成区域的波导。波导具有大的横截面面积，以实现等离子体的大区域。等离子体的均匀性和稳定性通过抑制混合传播模式的模式限制器来改善，否则传播模式容易发生在宽波导中。模式限制器由导电分配器组成，其在等离子体形成区域之前将波导横截面分成子导子阵列。

6. 发明授权

US5331191A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US5331191A
公开(公告)日：1994-07-19
申请号：US954142
申请日：1992-09-30
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L29/10
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区和非活性区域的全部表面部分中的方式，在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

7. 发明申请

US20100297783A1 Plasma Processing Method 审中-公开
标题翻译：等离子体处理方法
公开(公告)号：US20100297783A1
公开(公告)日：2010-11-25
申请号：US12849233
申请日：2010-08-03
申请人： Shoji IKUHARA , Daisuke Shiraishi , Hideyuki Yamamoto , Akira Kagoshima , Hiromichi Enami , Yosuke Karashima , Eiji Matsumoto
发明人： Shoji IKUHARA , Daisuke Shiraishi , Hideyuki Yamamoto , Akira Kagoshima , Hiromichi Enami , Yosuke Karashima , Eiji Matsumoto
IPC分类号： H01L21/302
CPC分类号： H01L21/67069 , H01J37/32935 , H01L21/67253
摘要： A method for performing a plasma process using a plasma processing apparatus which includes a vacuum process chamber, an exhaust device, a mass flow controller supplying a process gas, a stage electrode which receives and holds a workpiece by adsorption, a transfer device, and a high-frequency electrical source. The method includes a first step of performing the plasma process for the workpiece in the vacuum process chamber by a corresponding recipe of predetermined recipes, a second step of acquiring apparatus parameters showing the condition of the plasma processing apparatus when a specific recipe of the predetermined recipes is executed to diagnose whether the condition of the plasma processing apparatus is good or not based on the acquired apparatus parameters.
摘要翻译：一种使用等离子体处理装置进行等离子体处理的方法，所述等离子体处理装置包括真空处理室，排气装置，供给处理气体的质量流量控制器，通过吸附接收和保持工件的载物台电极，转印装置和高频电源。该方法包括：通过预定配方的相应配方对真空处理室中的工件进行等离子体处理的第一步骤;获取当预定配方的特定配方时显示等离子体处理装置的状态的装置参数的第二步骤被执行以基于所获取的装置参数来诊断等离子体处理装置的状况是否良好。

8. 发明申请

US20060260746A1 Plasma processing apparatus 审中-公开
标题翻译：等离子体处理装置
公开(公告)号：US20060260746A1
公开(公告)日：2006-11-23
申请号：US11199234
申请日：2005-08-09
申请人： Shoji Ikuhara , Daisuke Shiraishi , Hideyuki Yamamoto , Akira Kagoshima , Hiromichi Enami , Yosuke Karashima , Eiji Matsumoto
发明人： Shoji Ikuhara , Daisuke Shiraishi , Hideyuki Yamamoto , Akira Kagoshima , Hiromichi Enami , Yosuke Karashima , Eiji Matsumoto
IPC分类号： H01L21/306
CPC分类号： H01L21/67069 , H01J37/32935 , H01L21/67253
摘要： There is provided a preventive maintenance technique capable of diagnosing apparatus conditions without causing serious decrease in uptime ratio. A plasma process apparatus is composed of a plasma processing main frame, and an apparatus controller controlling the plasma processing main frame. The plasma processing main frame has a vacuum process chamber, an exhaust device evacuating the vacuum process chamber, a mass flow controller supplying a process gas into the vacuum process chamber, a stage electrode receiving a workpiece and holding it by adsorption, a high-frequency electrical source applying a high-frequency electrical power to the supplied process gas to generate plasma, and a transfer device placing the workpiece on the stage electrode and carrying out the processed workpiece. The apparatus controller controls the plasma processing main frame in accordance with a predetermined procedure and is provided with a diagnosis device which acquires a plurality of recipes for processing workpieces carried in the chamber and apparatus parameters of the plasma processing apparatus when a specific recipe of the above recipes is executed, whereby the condition of the plasma processing main frame is diagnosed based on the acquired apparatus parameters.
摘要翻译：提供了能够诊断装置条件而不引起正常运行时间比例严重降低的预防性维护技术。等离子体处理装置由等离子体处理主框架和控制等离子体处理主框架的装置控制器构成。等离子体处理主框架具有真空处理室，抽真空处理室的排气装置，向真空处理室供给工艺气体的质量流量控制器，接收工件并通过吸附保持其的阶段电极，高频电源向所提供的处理气体施加高频电力以产生等离子体;以及传送装置，将工件放置在平台电极上并且执行被处理的工件。设备控制器按照预定的步骤控制等离子体处理主框架，并且设置有诊断装置，该诊断装置获取用于处理在室中携带的工件的多个配方和等离子体处理装置的装置参数，当上述特定配方执行配方，由此基于所获取的装置参数来诊断等离子体处理主框架的状态。

9. 发明授权

US6127255A Semiconductor integrated circuit device, process for fabricating the same, and apparatus for fabricating the same 失效
标题翻译：半导体集成电路装置及其制造方法及其制造装置
公开(公告)号：US6127255A
公开(公告)日：2000-10-03
申请号：US943729
申请日：1997-10-03
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L21/4763 , H01L21/469
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由元件分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的有源区的主表面上形成MISFET。所公开的方法包括在包括最上面布线的布线上形成绝缘膜，最上面的布线在相邻最上布线之间具有间隙。绝缘膜包括在布线和相邻的最上布线之间的间隙中形成氧化硅膜，并且在氧化硅膜上形成氮化硅膜，通过等离子体化学气相沉积形成氮化硅膜。氧化硅膜形成为具有至少相邻最上面布线之间的间隙的一半的厚度，其中氮化硅膜比氧化硅膜厚。

10. 发明授权

US5739589A Semiconductor integrated circuit device process for fabricating the same and apparatus for fabricating the same 失效
标题翻译：用于制造该半导体集成电路器件的半导体集成电路器件及其制造方法
公开(公告)号：US5739589A
公开(公告)日：1998-04-14
申请号：US657194
申请日：1996-06-03
申请人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
发明人： Jun Sugiura , Osamu Tsuchiya , Makoto Ogasawara , Fumio Ootsuka , Kazuyoshi Torii , Isamu Asano , Nobuo Owada , Mitsuaki Horiuchi , Tsuyoshi Tamaru , Hideo Aoki , Nobuhiro Otsuka , Seiichirou Shirai , Masakazu Sagawa , Yoshihiro Ikeda , Masatoshi Tsuneoka , Toru Kaga , Tomotsugu Shimmyo , Hidetsugu Ogishi , Osamu Kasahara , Hiromichi Enami , Atsushi Wakahara , Hiroyuki Akimori , Sinichi Suzuki , Keisuke Funatsu , Yoshinao Kawasaki , Tunehiko Tubone , Takayoshi Kogano , Ken Tsugane
IPC分类号： G03F7/20 , G03F9/00 , H01L21/02 , H01L21/285 , H01L21/336 , H01L21/76 , H01L21/768 , H01L21/8238 , H01L21/8242 , H01L23/29 , H01L23/495 , H01L23/525 , H01L23/532 , H01L23/544 , H01L27/092 , H01L27/10 , H01L27/108 , H01L29/78 , H01L21/44 , H01L21/48
CPC分类号： H01L27/10852 , G03F7/70333 , G03F9/70 , H01L21/28512 , H01L21/76 , H01L21/76801 , H01L21/76804 , H01L21/76831 , H01L21/76834 , H01L21/76838 , H01L21/76843 , H01L21/76877 , H01L21/823807 , H01L23/291 , H01L23/4951 , H01L23/5258 , H01L23/532 , H01L23/544 , H01L27/0922 , H01L28/40 , H01L2223/54473 , H01L2224/05554 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45565 , H01L2224/4569 , H01L2224/48091 , H01L2224/48247 , H01L2224/4826 , H01L2224/73215 , H01L24/45 , H01L24/48 , H01L27/0928 , H01L27/10808 , H01L2924/00014 , H01L2924/01014 , H01L2924/01015 , H01L2924/01021 , H01L2924/01029 , H01L2924/01039 , H01L2924/01079 , H01L2924/04941 , H01L2924/12036 , H01L2924/12042 , H01L2924/12044 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/3025 , Y10S257/90
摘要： Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel stopper regions over the principal surface portions below the element separating insulating film of the substrate by introducing an impurity into all the surface portions including the active regions and the inactive regions of the substrate after the first mask and the second mask have been removed.
摘要翻译：这里公开了一种半导体集成电路器件制造工艺，用于在由分离绝缘膜和沟道阻挡区域形成的无源区域围绕的衬底的这些有源区的主表面上形成MISFET，其包括：形成步骤通过不可氧化掩模的第一掩模和顺序地在衬底的有源区的主表面上的蚀刻掩模; 分别通过比第一掩模的不可氧化掩模和蚀刻掩模更薄的不可氧化掩模在第一掩模的侧壁上自对准形成第二掩模的步骤; 通过使用第一掩模和第二掩模蚀刻衬底的非活性区的主表面的步骤; 通过使用第一掩模和第二掩模的氧化在衬底的无活性区域的主表面上形成元件分离绝缘膜的步骤; 以及通过在第一掩模之后将杂质引入到包括基板的有源区域和非活性区域的全部表面部分中而在基板的元件分离绝缘膜下方的主表面部分上形成沟道阻挡区域的步骤，面具已被删除。

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