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1. 发明授权

US06178132B1 Non-volatile integrated circuit having read while write capability using one address register 有权
标题翻译：具有读写能力的非易失性集成电路使用一个地址寄存器
公开(公告)号：US06178132B1
公开(公告)日：2001-01-23
申请号：US09391917
申请日：1999-09-09
申请人： Han Sung Chen , Chun Hsiung Hung , Kuo Yu Liao , Ray Lin Wan
发明人： Han Sung Chen , Chun Hsiung Hung , Kuo Yu Liao , Ray Lin Wan
IPC分类号： G11C800
CPC分类号： G11C16/08 , G11C2216/22
摘要： A non-volatile integrated circuit memory, such as a flash memory device based on floating gate transistor memory cells, with read while write capability is provided using a single address register. The integrated circuit includes at least two independent arrays of memory cells. During a program or an erase operation in one array on the non-volatile integrated circuit, a read operation can be executed in the other array on the same integrated circuit by bypassing the address register altogether, and allowing the register to remain in use by the program or erase operation. A bypass combinatorial logic path for the read process is coupled to the same address inputs as the address register, and operable in parallel with the registered address path.
摘要翻译：使用单个地址寄存器来提供非易失性集成电路存储器，例如基于浮栅晶体管存储器单元的闪速存储器件，具有读写能力。集成电路包括至少两个独立的存储单元阵列。在非易失性集成电路中的一个阵列中的程序或擦除操作期间，可以通过绕过地址寄存器来在同一集成电路上的另一个阵列中执行读取操作，并允许寄存器由编程或擦除操作。用于读取处理的旁路组合逻辑路径被耦合到与地址寄存器相同的地址输入，并且与注册的地址路径并行操作。

2. 发明授权

US5787039A Low current floating gate programming with bit-by-bit verification 失效
标题翻译：低电流浮栅编程与逐位验证
公开(公告)号：US5787039A
公开(公告)日：1998-07-28
申请号：US812615
申请日：1997-03-06
申请人： Han-Sung Chen , Tzeng-Huei Shiau , Yu-Shen Lin , Chung-Cheng Tsai , Jin-Lien Lin , Ray Lin Wan , Yuan-Chang Liu , Chun Hsiung Hung
发明人： Han-Sung Chen , Tzeng-Huei Shiau , Yu-Shen Lin , Chung-Cheng Tsai , Jin-Lien Lin , Ray Lin Wan , Yuan-Chang Liu , Chun Hsiung Hung
IPC分类号： G11C16/10 , G11C16/34 , G11C16/06
CPC分类号： G11C16/3486 , G11C16/10 , G11C16/3459 , G11C16/3468
摘要： A system for programming arrays of floating gate memory cells reduces programming current requirements, and reduces wordline and bitline stress during programming. A word-to-be-programmed into a floating gate memory array is divided into a plurality of smaller subwords. Only one subword is programmed at a time, thereby reducing programming current requirements. Additionally, subwords which are successfully programmed are not reprogrammed even if bits in other subwords do not program properly. This creates less wordline stress than previous systems which program an entire word at once, thereby requiring subwords which program successfully to be reprogrammed along with subwords which fail to program. Finally, within each subword only those bits which failed to program are reprogrammed, thereby reducing bitline stress during reprogramming for those bits which were successfully programmed.
摘要翻译：用于编程浮动栅极存储器单元阵列的系统减少了编程电流要求，并且减少了编程期间的字线和位线应力。要被编程到浮动存储器阵列中的字被分成多个较小的子字。一次只编写一个子字，从而减少编程电流的要求。此外，即使其他子词的位未正确编程，成功编程的子词也不会被重新编程。这与以前系统一样编制整个单词的系统产生较少的字面压力，从而要求程序成功地重新编程的子词以及不能编程的子词。最后，在每个子字中，只有那些无法编程的位被重新编程，从而在对已成功编程的那些位的重新编程期间减少位线应力。

3. 发明授权

US6104665A Enhanced word line driver to reduce gate capacitance for low voltage applications 有权
标题翻译：增强字线驱动器，以降低低电压应用的栅极电容
公开(公告)号：US6104665A
公开(公告)日：2000-08-15
申请号：US269983
申请日：1999-04-05
申请人： Chun Hsiung Hung , I-Long Lee , Tien-Shin Ho , Ray-Lin Wan
发明人： Chun Hsiung Hung , I-Long Lee , Tien-Shin Ho , Ray-Lin Wan
IPC分类号： G11C8/08 , G11C16/08 , G11C8/00
CPC分类号： G11C16/08 , G11C8/08
摘要： An enhanced word line driver circuit suitable for use on integrated circuits such as flash memory devices with voltage boosting includes a load reduction circuit. In response to a boosted voltage, the load reduction circuit decouples a gate capacitance load of deselected enhanced word line drivers from the boost voltage generator. The reduction of capacitive loading decreases power consumption and shortens the voltage boost time of the memory device.
摘要翻译： PCT No.PCT / US98 / 25809 Sec。 371日期1999年4月5日 102（e）1999年4月5日PCT 1998年12月4日提交适用于集成电路的增强型字线驱动电路，例如具有升压的闪存器件，包括负载降低电路。响应于升高的电压，负载降低电路将取消选择的增强型字线驱动器的栅极电容负载与升压电压发生器去耦。电容负载的降低降低了功耗并缩短了存储器件的升压时间。

4. 发明授权

US5963476A Fowler-Nordheim (F-N) tunneling for pre-programming in a floating gate memory device 失效
标题翻译： Fowler-Nordheim（F-N）隧道，用于在浮动栅极存储器件中进行预编程
公开(公告)号：US5963476A
公开(公告)日：1999-10-05
申请号：US975516
申请日：1997-11-12
申请人： Chun Hsiung Hung , Tzeng-Huei Shiau , Yao-Wu Cheng , I-Long Lee , Fuchia Shone , Ray-Lin Wan
发明人： Chun Hsiung Hung , Tzeng-Huei Shiau , Yao-Wu Cheng , I-Long Lee , Fuchia Shone , Ray-Lin Wan
IPC分类号： G11C16/02 , G11C16/04 , G11C16/16 , G11C16/34 , H01L27/115 , G11C16/06
CPC分类号： G11C16/107 , G11C16/0416 , G11C16/16 , G11C16/3454 , G11C16/3459 , H01L27/115
摘要： A new flash memory cell structure and operational bias is based on the use of a triple well flash memory cell which allows pre-programming by Fowler Nordheim (F-N) tunneling over blocks of cells at a time. The floating gate memory cell is made in a semiconductor substrate having a first conductivity type, such as p-type. A first well within the substrate by having a second conductivity type different than the first conductivity type is included. A second well within the first well is also included having the first conductivity type. A drain and a source are formed in the second well having the second conductivity type, and spaced away from one another to define a channel area between the drain and the source. A floating gate and control gate structure is included over the channel area. The floating gate memory cell is coupled with circuits that induce F-N tunneling of electrons out of the floating gate into the channel area of the substrate for erasing by applying a positive voltage to the second well, such as a voltage higher than the supply voltage, applying a positive voltage to the first well, which is substantially equal to the positive voltage of the second well, applying a negative voltage to the control gate of the cell, while the substrate is grounded. A block wide pre-program operation involves F-N tunneling of electrons into the floating gate from the channel area, using a negative voltage in the second well.
摘要翻译：新的闪存单元结构和操作偏置是基于使用三阱闪存单元，其允许Fowler Nordheim（F-N）一次在单元格块上进行预编程。浮栅存储单元由具有第一导电类型的半导体衬底制成，例如p型。包括具有不同于第一导电类型的第二导电类型的衬底内的第一阱。还包括第一阱中的第二阱具有第一导电类型。在具有第二导电类型的第二阱中形成漏极和源极，并且彼此间隔开以限定漏极和源极之间的沟道区域。通道区域中包括浮动栅极和控制栅极结构。浮动栅极存储单元与电路耦合，该电路通过向第二阱施加正电压，例如高于电源电压的电压，施加电压，使电子从浮动栅极进入隧道区域进入衬底的通道区域以进行擦除与第一阱的正电压相比，其基本上等于第二阱的正电压，而在衬底接地时，向电池的控制栅极施加负电压。块宽的预编程操作涉及使用第二阱中的负电压将电子从沟道区域F-N隧穿到浮置栅极。

5. 发明授权

US08508993B2 Method and apparatus of performing an erase operation on a memory integrated circuit 有权
标题翻译：在存储器集成电路上执行擦除操作的方法和装置
公开(公告)号：US08508993B2
公开(公告)日：2013-08-13
申请号：US13567817
申请日：2012-08-06
申请人： Yi-Fan Chang , Su-chueh Lo , Cheng-Ming Yi , Ta Kang Chu , Chu Ching Wu , Kuo Yu Liao , Ken Hui Chen , Kuen Long Chang , Chun Hsiung Hung
发明人： Yi-Fan Chang , Su-chueh Lo , Cheng-Ming Yi , Ta Kang Chu , Chu Ching Wu , Kuo Yu Liao , Ken Hui Chen , Kuen Long Chang , Chun Hsiung Hung
IPC分类号： G11C11/34
CPC分类号： G11C11/5635 , G11C16/0483 , G11C16/3418
摘要： Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.
摘要翻译：各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

6. 发明授权

US07236404B2 Structures and methods for enhancing erase uniformity in an NROM array 有权
公开(公告)号：US07236404B2
公开(公告)日：2007-06-26
申请号：US11210425
申请日：2005-08-24
申请人： Ching Chung Lin , Ken Hui Chen , Nai Ping Kuo , Han Sung Chen , Chun Hsiung Hung , Wen Yi Hsieh
发明人： Ching Chung Lin , Ken Hui Chen , Nai Ping Kuo , Han Sung Chen , Chun Hsiung Hung , Wen Yi Hsieh
IPC分类号： G11C11/34
CPC分类号： G11C16/0491 , G11C16/0475 , G11C16/14
摘要： A virtual ground NROM array has a matrix of NROM cells in which during an erase operation the non-erasing side of NROM cells are connected to a common node for enhancing the erase uniformity of the NROM array. If an operation requests erasing on the left side of NROM cells, a positive voltage is supplied from an internal power supply to the left side for each of the NROM cells, and the right side for each of the NROM cells is discharged to a common node. If an operation requests erasing the right side of NROM cells, a positive voltage is supplied from the internal power supply to the right side for each of the NROM cells, and the right side for each of the NROM cells is connected to the common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally. In an alternative embodiment, non-erasing sides of NROM cells in the NROM array are connected to a current source during an erase operation for enhancing the erase uniformity of the NROM array. If an operation requests erasing the left side of NROM cells, a positive voltage is supplied from an internal power supply to the left side for each of the NROM cells, and the right side for each of the NROM cells is discharged to a current source. If an operation requests erasing the right side of NROM cells, a positive voltage is supplied from the internal power supply to the right side for each of the NROM cells, and the right side for each of the NROM cells is connected to the current source.

7. 发明授权

US07423913B2 Structures and methods for enhancing erase uniformity in a nitride read-only memory array 有权
标题翻译：用于增强氮化物只读存储器阵列中的擦除均匀性的结构和方法
公开(公告)号：US07423913B2
公开(公告)日：2008-09-09
申请号：US11695668
申请日：2007-04-03
申请人： Ching Chung Lin , Ken Hui Chen , Nai Ping Kuo , Han Sung Chen , Chun Hsiung Hung , Wen Yi Hsieh
发明人： Ching Chung Lin , Ken Hui Chen , Nai Ping Kuo , Han Sung Chen , Chun Hsiung Hung , Wen Yi Hsieh
IPC分类号： G11C11/34
CPC分类号： G11C16/0491 , G11C16/0475 , G11C16/14
摘要： A virtual ground nitride read-only memory array has a matrix of nitride read-only memory cells in which during an erase operation the non-erasing side of nitride read-only memory cells are connected to a common node for enhancing the erase uniformity of the nitride read-only memory array. If an operation requests erasing on the left side of nitride read-only memory cells, a positive voltage is supplied from an internal power supply to the left side for each of the nitride read-only memory cells, and the right side for each of the nitride read-only memory cells is discharged to a common node. The voltage level of the common mode is selected to be sufficiently high in order to prevent from punch through while at the same time sufficiently low to maintain the lateral electric field for erase operation to function optimally.
摘要翻译：虚拟氮化物只读存储器阵列具有氮化物只读存储器单元的矩阵，其中在擦除操作期间，氮化物只读存储器单元的非擦除侧连接到公共节点，以增强擦除均匀性氮化物只读存储器阵列。如果操作要求在氮化物只读存储单元的左侧擦除，则从内部电源向氮化物只读存储单元中的每一个向左侧提供正电压，并且对于每个氮化物只读存储单元被放电到公共节点。选择共模的电压足够高以防止穿通，同时足够低以保持用于擦除操作的横向电场最佳地起作用。

8. 发明授权

US07595682B2 Multi-stage charge pump without threshold drop with frequency modulation between embedded mode operations 有权
标题翻译：多级电荷泵，无嵌入式模式操作之间的频率调制门限下降
公开(公告)号：US07595682B2
公开(公告)日：2009-09-29
申请号：US11064920
申请日：2005-02-24
申请人： Yufe Feng Lin , Yu Shen Lin , Roger Chen , Chun Hsiung Hung
发明人： Yufe Feng Lin , Yu Shen Lin , Roger Chen , Chun Hsiung Hung
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2003/075
摘要： A multimode charge pump circuit has a single charge pump that is responsive to a set of clock signals. The set of clock signals is provided in a first mode with a variable frequency according to a first function of the supply potential and temperature, and in a second mode with a variable frequency according to a second function of the supply potential and temperature. Circuitry configures all of the plurality of stages in series during the first mode in order to produce a higher voltage output, and configures a subset of the plurality of stages in series, while disabling the other stages, during the second mode in order to produce a lower voltage output. A precharge circuit is provided that operates as a supply node in the second mode, and as a precharge/clamp in the first mode.
摘要翻译：多模电荷泵电路具有响应于一组时钟信号的单个电荷泵。根据电源电位和温度的第一功能，在第一模式下以一个可变频率提供一组时钟信号，并且根据电源电位和温度的第二功能以第二种可变频率提供时钟信号。电路在第一模式期间配置串联的所有多个级，以便产生较高的电压输出，并且在第二模式期间在禁用其它级的同时，在多个级的串联中配置子集，以产生较低的电压输出。提供预充电电路，其在第二模式中作为供电节点工作，并且作为第一模式中的预充电/钳位。

9. 发明授权

US07580302B2 Parallel threshold voltage margin search for MLC memory application 有权
标题翻译：并行阈值电压裕度搜索MLC存储器应用
公开(公告)号：US07580302B2
公开(公告)日：2009-08-25
申请号：US11551974
申请日：2006-10-23
申请人： Wen Chiao Ho , Chin Hung Chang , Cheng-Chi Liu , Kuen-Long Chang , Chun Hsiung Hung
发明人： Wen Chiao Ho , Chin Hung Chang , Cheng-Chi Liu , Kuen-Long Chang , Chun Hsiung Hung
IPC分类号： G11C29/00
CPC分类号： G11C29/50 , G11C11/5642 , G11C16/04 , G11C29/50004 , G11C2211/5634 , G11C2211/5644
摘要： A method for determining read voltage margins in a memory array compares as-read sum codes generated from data read from the memory array with expected sum codes generated from the loaded data. The read voltage (Vt) is stepped and the as-read sum codes are compared to the expected sum codes to determine the Vt range(s) that provides matching sum codes. Multiple read voltage margins (i.e. the read voltage margins between multiple programming levels of the MLC memory array) are determined in a parallel fashion as Vt is stepped across its range.
摘要翻译：用于确定存储器阵列中的读取电压余量的方法将从存储器阵列读取的数据产生的读取和编码与从加载数据生成的预期总和进行比较。读取电压（Vt）是步进的，将读取的和码与预期的和码进行比较，以确定提供匹配和码的Vt范围。当Vt跨过其范围时，以并行方式确定多个读取电压余量（即，MLC存储器阵列的多个编程电平之间的读取电压余量）。

10. 发明授权

US08982640B2 Method and apparatus for reducing erase disturb of memory by using recovery bias 有权
标题翻译：通过使用恢复偏压来减少存储器的擦除干扰的方法和装置
公开(公告)号：US08982640B2
公开(公告)日：2015-03-17
申请号：US13426985
申请日：2012-03-22
申请人： Chun Hsiung Hung , Bo-Chang Wu , Kuen-Long Chang , Ken-Hui Chen
发明人： Chun Hsiung Hung , Bo-Chang Wu , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/3431 , G11C16/14 , G11C16/3418 , G11C16/344
摘要： A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.
摘要翻译：非易失性存储器阵列被分成多个存储器组。非易失性存储器阵列接收擦除命令以擦除第一组存储器组，而不是第二组存储器组。控制电路响应于擦除命令来擦除第一组存储器组，通过应用恢复偏压布置来调整第二组存储器组的至少一个存储器组中的存储器单元的阈值电压。通过将恢复偏压装置应用于第二组存储器组的至少一个存储器组中的存储器单元，至少部分地在恢复偏压装置期间校正擦除干扰。

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