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1. 发明申请

US20120262987A1 METHOD AND APPARATUS FOR LEAKAGE SUPPRESSION IN FLASH MEMORY IN RESPONSE TO EXTERNAL COMMANDS 有权
标题翻译： FLASH存储器中对外部命令的泄漏抑制方法和装置
公开(公告)号：US20120262987A1
公开(公告)日：2012-10-18
申请号：US13308266
申请日：2011-11-30
申请人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
发明人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
IPC分类号： G11C16/10
CPC分类号： G11C16/3409 , G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.
摘要翻译：本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。该设备还包括用于从存储设备外部的源接收命令的命令接口。该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

2. 发明申请

US20080282107A1 Method and Apparatus for Repairing Memory 有权
标题翻译：用于修复存储器的方法和装置
公开(公告)号：US20080282107A1
公开(公告)日：2008-11-13
申请号：US11745244
申请日：2007-05-07
申请人： Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Su-Chueh Lo
发明人： Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Su-Chueh Lo
IPC分类号： G06F11/26
CPC分类号： G11C29/56 , G11C29/56008 , G11C29/88
摘要： Methods and apparatuses are disclosed in which a repair instruction, such as from a tester, causes an integrated circuit undergoing testing to substitute defective locations of a first set of memory cells in the integrated circuit with a second set of memory cells in the integrated circuit, despite the repair instruction omitting the defective locations of the first set of memory cells of the integrated circuit.
摘要翻译：公开了一种方法和装置，其中诸如来自测试者的修复指令使得正在进行测试的集成电路用集成电路中的第二组存储器单元替换集成电路中的第一组存储器单元的缺陷位置，尽管修复指令省略了集成电路的第一组存储单元的缺陷位置。

3. 发明申请

US20080186770A1 Non-volatile memory device and method of compensating leakage reading current of a non-volatile memory array 有权
标题翻译：非易失性存储器件和补偿非易失性存储器阵列泄漏读取电流的方法
公开(公告)号：US20080186770A1
公开(公告)日：2008-08-07
申请号：US12068195
申请日：2008-02-04
申请人： Chun-Hsiung Hung , Su-Chueh Lo , Han-Sung Chen
发明人： Chun-Hsiung Hung , Su-Chueh Lo , Han-Sung Chen
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0491 , G11C16/26
摘要： A non-volatile memory package includes a non-volatile memory array having a plurality of transistors that are electrically coupled in series, each of the transistors having an input terminal and an output terminal such that the output terminal of one of the transistors is coupled to the input terminal of a next transistor in a downstream direction. A read voltage supply supplies a voltage to the input terminal of a selected transistor of the plurality of transistors, to induce a cell current between the input terminal and the output terminal of the selected transistor. A bit sensor receives and evaluates a read current from the output terminal of the selected transistor. A shielding voltage applicator applies a voltage to the input terminal or the output terminal of a downstream transistor of the plurality of transistors, the downstream transistor being in the downstream direction from the selected transistor.
摘要翻译：非易失性存储器封装包括具有串联电耦合的多个晶体管的非易失性存储器阵列，每个晶体管具有输入端和输出端，使得晶体管中的一个的输出端耦合到下游晶体管的输入端子沿下游方向。读取电压电源向多个晶体管中所选择的晶体管的输入端提供电压，以在所选择的晶体管的输入端和输出端之间感应出电池电流。位传感器从所选择的晶体管的输出端接收并评估读取电流。屏蔽电压施加器对多个晶体管的下游晶体管的输入端子或输出端子施加电压，下游晶体管处于从所选晶体管的下游方向。

4. 发明授权

US08977912B2 Method and apparatus for repairing memory 有权
标题翻译：修复记忆体的方法和装置
公开(公告)号：US08977912B2
公开(公告)日：2015-03-10
申请号：US11745244
申请日：2007-05-07
申请人： Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Su-Chueh Lo
发明人： Chun-Hsiung Hung , Han-Sung Chen , Nai-Ping Kuo , Su-Chueh Lo
IPC分类号： G11C29/24 , G11C29/56 , G11C29/00 , G11C29/54
CPC分类号： G11C29/56 , G11C29/56008 , G11C29/88
摘要： Methods and apparatuses are disclosed in which a repair instruction, such as from a tester, causes an integrated circuit undergoing testing to substitute defective locations of a first set of memory cells in the integrated circuit with a second set of memory cells in the integrated circuit, despite the repair instruction omitting the defective locations of the first set of memory cells of the integrated circuit.
摘要翻译：公开了一种方法和装置，其中诸如来自测试者的修复指令使得正在进行测试的集成电路用集成电路中的第二组存储器单元替换集成电路中的第一组存储器单元的缺陷位置，尽管修复指令省略了集成电路的第一组存储单元的缺陷位置。

5. 发明授权

US08929139B2 Method and apparatus for leakage suppression in flash memory 有权
标题翻译：闪存中泄漏抑制的方法和装置
公开(公告)号：US08929139B2
公开(公告)日：2015-01-06
申请号：US13308301
申请日：2011-11-30
申请人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
发明人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
IPC分类号： G11C11/34 , G11C16/04 , G11C16/34 , G11C11/56 , G11C16/14
CPC分类号： G11C16/3409 , G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block.
摘要翻译：本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。在一个实施例中，描述了一种闪存器件，其包括包括多个存储器单元块的存储器阵列。该装置还包括执行泄漏抑制处理的控制器。泄漏抑制过程包括确定给定的存储单元块包括一个或多个过擦除存储器单元。在确定时，泄漏抑制处理还包括执行软程序操作以增加给定块中的被擦除的存储器单元的阈值电压。

6. 发明申请

US20130100745A1 Method and Apparatus of Performing An Erase Operation On A Memory Integrated Circuit 有权
标题翻译：在存储器集成电路中执行擦除操作的方法和装置
公开(公告)号：US20130100745A1
公开(公告)日：2013-04-25
申请号：US13708102
申请日：2012-12-07
申请人： Yi-Fan Chang , Cheng Ming Yih , Su-chueh Lo , Jian Shing Liu , Kuen Long Chang , Chun-Hsiung Hung
发明人： Yi-Fan Chang , Cheng Ming Yih , Su-chueh Lo , Jian Shing Liu , Kuen Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/14
CPC分类号： G11C16/14 , G11C16/344 , G11C16/3477
摘要： Various discussed approaches include an improved grouping of edge word lines and center word lines of an erase group during erase verify and erase sub-operations of an erase operation. In another approach, changed voltage levels of edge word lines to address the over-erase issue of the erase group, and also improve erase time performance. Another approach uses dummy word lines.
摘要翻译：各种讨论的方法包括在擦除验证和擦除擦除操作的子操作期间改进擦除组的边缘字线和中心字线的分组。在另一种方法中，改变边缘字线的电压电平以解决擦除组的过擦除问题，并且还提高擦除时间性能。另一种方法使用虚拟字线。

7. 发明申请

US20130027120A1 Standby Charge Pump System 有权
标题翻译：待机充电泵系统
公开(公告)号：US20130027120A1
公开(公告)日：2013-01-31
申请号：US13330165
申请日：2011-12-19
申请人： Su-Chueh Lo , Wenming Hsu , Wu-Chin Peng
发明人： Su-Chueh Lo , Wenming Hsu , Wu-Chin Peng
IPC分类号： G05F3/02
CPC分类号： G11C5/145 , G11C5/148
摘要： In one aspect, a charge pump output of a charge pump is coupled to a capacitor of a voltage shifter. The output of the voltage shifter causes pump control logic to enable the charge pump. In another aspect, a transistor in saturation has a drain terminal coupled to a charge pump output and a source terminal coupled to an output mode providing a word line read voltage.
摘要翻译：一方面，电荷泵的电荷泵输出耦合到电压移位器的电容器。电压转换器的输出使泵控制逻辑使能电荷泵。在另一方面，饱和晶体管具有耦合到电荷泵输出的漏极端子和耦合到提供字线读取电压的输出模式的源极端子。

8. 发明申请

US20120075943A1 Method and Apparatus for Memory Repair With Redundant Columns 审中-公开
标题翻译：用冗余列进行内存修复的方法和装置
公开(公告)号：US20120075943A1
公开(公告)日：2012-03-29
申请号：US12893235
申请日：2010-09-29
申请人： Chia-Jung Chen , Su-Chueh Lo , Chin-Hung Chang , Chen-Chia Fan , Kuen-Long Chang
发明人： Chia-Jung Chen , Su-Chueh Lo , Chin-Hung Chang , Chen-Chia Fan , Kuen-Long Chang
IPC分类号： G11C29/04
CPC分类号： G11C29/808
摘要： A first redundant column is used to repair multiple defects in an array of memory cells. The defects include at least a first defect and a second defect in different main columns of a plurality of main columns in the array. However, all of the multiple defects repaired by the first redundant column are not required to be in different main columns. The array is arranged into a plurality of rows accessed by row addresses and the plurality of main columns accessed by column addresses.
摘要翻译：第一冗余列用于修复存储器单元阵列中的多个缺陷。缺陷包括阵列中的多个主列的不同主列中的至少第一缺陷和第二缺陷。然而，由第一冗余列修复的所有多个缺陷不需要在不同的主列中。该阵列被布置成由行地址和由列地址访问的多个主列访问的多行。

9. 发明申请

US20120051142A1 Soft Program Method and Computer Redable Medium Thereof 有权
标题翻译：软件程序方法和计算机可重复介质
公开(公告)号：US20120051142A1
公开(公告)日：2012-03-01
申请号：US12868870
申请日：2010-08-26
申请人： Chin-Hung Chang , Su-Chueh Lo , Chen-Chia Fan , Chia-Feng Cheng
发明人： Chin-Hung Chang , Su-Chueh Lo , Chen-Chia Fan , Chia-Feng Cheng
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/3404 , G11C16/10
摘要： A soft program method is provided for recovering memory cells of a memory array. In an embodiment, the method includes the following steps. Memory blocks of the memory array are soft programmed with first bias voltage. A selected memory unit within a selected memory block is then soft programmed with second bias voltage. Next, whether a judging criterion is met is determined. If not, the method is repeated from the step of soft programming with the second bias voltage; if so, whether the selected unit is a last memory unit is determined. If the selected unit is not the last memory unit, other memory unit is assigned as the selected memory unit and the method is repeated from the step of soft programming with the second bias voltage. When the selected unit is the last memory unit, the memory array is bit-by-bit soft programmed with a third bias voltage.
摘要翻译：提供了一种用于恢复存储器阵列的存储单元的软程序方法。在一个实施例中，该方法包括以下步骤。存储器阵列的存储块通过第一偏置电压进行软编程。所选择的存储器块中的选定的存储器单元随后用第二偏置电压进行软编程。接下来，确定是否满足判断标准。如果没有，则从具有第二偏置电压的软编程步骤重复该方法; 如果是，则确定所选择的单元是否是最后的存储单元。如果所选择的单元不是最后一个存储单元，则将其他存储单元分配为所选存储单元，并从第二偏置电压的软编程步骤重复该方法。当所选单元是最后一个存储单元时，存储器阵列以第三偏置电压进行逐位软编程。

10. 发明申请

US20110317493A1 Method and Apparatus of Performing An Erase Operation on a Memory Integrated Circuit 有权
标题翻译：在存储器集成电路上执行擦除操作的方法和装置
公开(公告)号：US20110317493A1
公开(公告)日：2011-12-29
申请号：US12826280
申请日：2010-06-29
申请人： Yi-Fan Chang , Su-chueh Lo , Cheng Ming Yih , Ta Kang Chu , Chu Ching Wu , Kuo Yu Liao , Ken Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yi-Fan Chang , Su-chueh Lo , Cheng Ming Yih , Ta Kang Chu , Chu Ching Wu , Kuo Yu Liao , Ken Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C16/04
CPC分类号： G11C11/5635 , G11C16/0483 , G11C16/3418
摘要： Various discussed approaches improve the over erase issue and the coupling effect, and include (A) multilevel contacts between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line; (B) a sufficient separation distance between (i) the first outer selected word line of an erase group, and (ii) the first unselected word line outside the ease group neighboring the first outer selected word line. These are examples of electrically isolating (i) the first outer selected word line of an erase group, from (ii) the first unselected word line outside the ease group neighboring the first outer selected word line.
摘要翻译：各种讨论的方法改进了过度擦除问题和耦合效应，并且包括（A）（i）擦除组的第一外部选定字线之间的多电平接触，以及（ii）与易失性组相邻的第一未选择字线第一外选字线; （B）在（i）擦除组的第一外部选择字线之间的足够的间隔距离，和（ii）与第一外部选择字线相邻的容易组之外的第一未选择字线。这些是将（i）擦除组的第一外部选择的字线从（ii）与第一外部选择字线相邻的易用组之外的第一未选择字线电隔离的示例。

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