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1. 发明申请

US20110069571A1 Word Line Decoder Circuit Apparatus and Method 有权
标题翻译：字线解码器电路设备及方法
公开(公告)号：US20110069571A1
公开(公告)日：2011-03-24
申请号：US12816960
申请日：2010-06-16
申请人： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C7/00 , G11C8/10
CPC分类号： G11C16/16
摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.
摘要翻译：该技术的一个实施例是一种装置，存储器集成电路。存储器集成电路具有字线地址解码电路。该电路允许选择单个字线以具有擦除电压。解码器电路包括反相器和逻辑。逆变器具有输入和控制字线的输出以执行擦除操作。输入的电压范围在第一参考电压和第二电压基准之间延伸。电压基准的示例是电压源和地。在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。

2. 发明授权

US08982640B2 Method and apparatus for reducing erase disturb of memory by using recovery bias 有权
标题翻译：通过使用恢复偏压来减少存储器的擦除干扰的方法和装置
公开(公告)号：US08982640B2
公开(公告)日：2015-03-17
申请号：US13426985
申请日：2012-03-22
申请人： Chun Hsiung Hung , Bo-Chang Wu , Kuen-Long Chang , Ken-Hui Chen
发明人： Chun Hsiung Hung , Bo-Chang Wu , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/3431 , G11C16/14 , G11C16/3418 , G11C16/344
摘要： A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.
摘要翻译：非易失性存储器阵列被分成多个存储器组。非易失性存储器阵列接收擦除命令以擦除第一组存储器组，而不是第二组存储器组。控制电路响应于擦除命令来擦除第一组存储器组，通过应用恢复偏压布置来调整第二组存储器组的至少一个存储器组中的存储器单元的阈值电压。通过将恢复偏压装置应用于第二组存储器组的至少一个存储器组中的存储器单元，至少部分地在恢复偏压装置期间校正擦除干扰。

3. 发明授权

US08638636B2 Word line decoder circuit apparatus and method 有权
标题翻译：字线解码电路装置及方法
公开(公告)号：US08638636B2
公开(公告)日：2014-01-28
申请号：US12816960
申请日：2010-06-16
申请人： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Shin-Jang Shen , Bo-Chang Wu , Chuan Ying Yu , Ken-Hui Chen , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G11C8/00
CPC分类号： G11C16/16
摘要： One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.
摘要翻译：该技术的一个实施例是一种装置，存储器集成电路。存储器集成电路具有字线地址解码电路。该电路允许选择单个字线以具有擦除电压。解码器电路包括反相器和逻辑。逆变器具有输入和控制字线的输出以执行擦除操作。输入的电压范围在第一参考电压和第二电压基准之间延伸。电压基准的示例是电压源和地。在一些实施例中，该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。解码器的逻辑电路由字线地址控制，以在擦除操作期间确定反相器的输入值。

4. 发明授权

US08825978B2 Memory apparatus 有权
标题翻译：存储设备
公开(公告)号：US08825978B2
公开(公告)日：2014-09-02
申请号：US13584393
申请日：2012-08-13
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
IPC分类号： G06F12/00 , G06F13/42 , G11C29/00
CPC分类号： G11C7/1072 , G11C7/1066 , G11C7/222 , G11C2207/104
摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.
摘要翻译：存储装置包括主机装置和从装置。主机设备存储验证数据。从设备包括存储单元，控制单元和逻辑单元。控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。前导码数据和存储数据根据内部时钟信号发送。主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

5. 发明申请

US20120057410A1 Method and Apparatus for the Erase Suspend Operation 有权
标题翻译：擦除挂起操作的方法和装置
公开(公告)号：US20120057410A1
公开(公告)日：2012-03-08
申请号：US12875003
申请日：2010-09-02
申请人： Chuan-Ying Yu , Ken-Hui Chen , Chun-Hsiung Hung , Kuen-Long Chang
发明人： Chuan-Ying Yu , Ken-Hui Chen , Chun-Hsiung Hung , Kuen-Long Chang
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/345 , G11C16/3454
摘要： Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.
摘要翻译：非易失性存储器的各个方面具有改进的擦除暂停过程。偏移布置被施加到经历由擦除暂停过程中断的擦除过程的擦除扇区的字线。结果，由于擦除扇区的任何被擦除的非易失性存储单元的漏电流减少，因此在诸如读操作或程序操作的擦除暂停期间执行的另一操作具有更精确的结果。

6. 发明授权

US08482987B2 Method and apparatus for the erase suspend operation 有权
公开(公告)号：US08482987B2
公开(公告)日：2013-07-09
申请号：US12875003
申请日：2010-09-02
申请人： Chuan-Ying Yu , Ken-Hui Chen , Chun-Hsiung Hung , Kuen-Long Chang
发明人： Chuan-Ying Yu , Ken-Hui Chen , Chun-Hsiung Hung , Kuen-Long Chang
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/345 , G11C16/3454
摘要： Various aspects of a nonvolatile memory have an improved erase suspend procedure. A bias arrangement is applied to word lines of an erase sector undergoing an erase procedure interrupted by an erase suspend procedure. As a result, another operation performed during erase suspend, such as a read operation or program operation, has more accurate results due to decreased leakage current from any over-erased nonvolatile memory cells of the erase sector.

7. 发明授权

US06255900B1 Rapid on chip voltage generation for low power integrated circuits 有权
标题翻译：用于低功率集成电路的快速片上电压产生
公开(公告)号：US06255900B1
公开(公告)日：2001-07-03
申请号：US09284435
申请日：1999-04-12
申请人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , Tien-Shin Ho , I-Long Lee , Tzeng-Hei Shiau , Ray-Lin Wan
发明人： Kuen-Long Chang , Chun-Hsiung Hung , Ken-Hui Chen , Tien-Shin Ho , I-Long Lee , Tzeng-Hei Shiau , Ray-Lin Wan
IPC分类号： G05F110
CPC分类号： G11C16/30 , G05F3/242 , G11C5/145 , G11C16/08 , H02M3/07
摘要： An on chip voltage generation circuit is provided suitable for use on integrated circuits such as flash memory devices with a low power supply voltage (e.g., 2.7 to 3.6 volts). A voltage boost circuit is coupled to the supply voltage input and to a boost signal, which boosts the on-chip voltage at a node on the integrated circuit in response to a transition of the boost signal. The voltage boost circuit has a first mode which in response to the transition boosts the on-chip voltage at a first rate of boosting until a first threshold, and a second mode which in response to the transition boosts the on-chip voltage at a second rate of boosting until a second threshold. The second rate of boosting in the preferred system is slower than the first rate of boosting. A detection circuit is coupled to the node on the integrated circuit which receives the on-chip voltage, and to the voltage boost circuit. The detection circuit signals the voltage boost circuit when the node reaches the first threshold, and signals the voltage boost circuit when the node reaches the second threshold. According to one aspect of the invention, the first threshold is reached within less than 5 nanoseconds, and more preferably about 2 nanoseconds, or less, of the transition in the boost signal.
摘要翻译：提供了适用于具有低电源电压（例如，2.7至3.6伏特）的闪存器件的集成电路的片上电压产生电路。电压升压电路耦合到电源电压输入和升压信号，该升压信号响应于升压信号的转变而升高集成电路上的节点上的片内电压。升压电路具有第一模式，其响应于转换而以第一升压速率提升片上电压直到第一阈值，并且响应于转换的第二模式将片上电压提升到第二阈值升压速率直到第二个阈值。优选系统中的第二次升压速度比第一次升压速率慢。检测电路耦合到接收片上电压的集成电路上的节点和电压升压电路。当节点达到第一阈值时，检测电路向升压电路发信号，当节点达到第二阈值时，信号通知升压电路。根据本发明的一个方面，在升压信号中的转变的小于5纳秒，更优选约2纳秒或更小的范围内达到第一阈值。

8. 发明授权

US08717813B2 Method and apparatus for leakage suppression in flash memory in response to external commands 有权
标题翻译：响应于外部命令，闪存中泄漏抑制的方法和装置
公开(公告)号：US08717813B2
公开(公告)日：2014-05-06
申请号：US13308266
申请日：2011-11-30
申请人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
发明人： Nai-Ping Kuo , Su-Chueh Lo , Kuen-Long Chang , Chun-Hsiung Hung , Chia-Feng Cheng , Ken-Hui Chen , Yu-Chen Wang
IPC分类号： G11C11/34
CPC分类号： G11C16/3409 , G11C11/5635 , G11C16/0483 , G11C16/14
摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device includes a memory array including a plurality of blocks of memory cells. The device also includes a command interface to receive a command from a source external to the memory device. The device also includes a controller including logic to perform a leakage-suppression process in response to the command. The leakage-suppression process includes performing a soft program operation to increase a threshold voltage of one or more over-erased memory cells in a given block of memory cells and establish an erased state.
摘要翻译：本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。在一个实施例中，闪存器件包括包括多个存储单元块的存储器阵列。该设备还包括用于从存储设备外部的源接收命令的命令接口。该装置还包括控制器，其包括响应于该命令执行泄漏抑制处理的逻辑。泄漏抑制处理包括执行软程序操作以增加给定的存储单元块中的一个或多个过擦除存储器单元的阈值电压并建立擦除状态。

9. 发明授权

US08643404B1 Self-calibration of output buffer driving strength 有权
标题翻译：输出缓冲器自校准驱动强度
公开(公告)号：US08643404B1
公开(公告)日：2014-02-04
申请号：US13556579
申请日：2012-07-24
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： H03K3/00
CPC分类号： H03K17/145 , H03K19/00384 , H03K2005/00026
摘要： An integrated circuit includes an output buffer and a control circuit. The output buffer has a signal input, a signal output, and a set of control inputs. The output buffer has an output buffer delay, and a driving strength adjustable in response to control signals applied to the set of control inputs. The control circuit is connected to the set of control inputs of the output buffer. The control circuit uses first and second timing signals to generate the control signals, and includes a reference delay circuit that generates the first timing signal with a reference delay, and a delay emulation circuit that generates the second timing signal with an emulation delay that correlates with the output buffer delay.
摘要翻译：集成电路包括输出缓冲器和控制电路。输出缓冲器具有信号输入，信号输出和一组控制输入。输出缓冲器具有输出缓冲器延迟，并且响应于施加到该组控制输入的控制信号而可调整驱动强度。控制电路连接到输出缓冲器的一组控制输入。控制电路使用第一和第二定时信号来产生控制信号，并且包括产生具有参考延迟的第一定时信号的参考延迟电路，以及延迟仿真电路，其产生与第二定时信号相关的仿真延迟输出缓冲区延迟。

10. 发明申请

US20130242665A1 Method and Apparatus for Shortened Erase Operation 有权
标题翻译：用于缩短擦除操作的方法和装置
公开(公告)号：US20130242665A1
公开(公告)日：2013-09-19
申请号：US13536555
申请日：2012-06-28
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/14 , G11C29/34 , G11C2029/2602
摘要： A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.
摘要翻译：非易失性存储器阵列具有不同持续时间的多个擦除过程。可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

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