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1. 发明授权

US07586802B2 Memory, bit-line pre-charge circuit and bit-line pre-charge method 有权
标题翻译：存储器，位线预充电电路和位线预充电方法
公开(公告)号：US07586802B2
公开(公告)日：2009-09-08
申请号：US12027333
申请日：2008-02-07
申请人： Jer-Hau Hsu , Fu-Nian Liang , Yufe-Feng Lin
发明人： Jer-Hau Hsu , Fu-Nian Liang , Yufe-Feng Lin
IPC分类号： G11C7/00
CPC分类号： G11C7/12
摘要： A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp transistor. The clamp transistor has a first end, a second end and a control end. The inverter has an input end electrically connected to the second end of the clamp transistor and an output end electrically connected to the control end of the clamp transistor. The bit line is electrically connected to the second end of the clamp transistor and the input end of the inverter and has a bit-line voltage thereon. The pre-charge path is electrically connected to the first end of the clamp transistor through a node having a sensing voltage thereon. The detector and controller circuit is electrically connected to the first end of the clamp transistor and the pre-charge path for detecting the sensing voltage in order to open the pre-charge path to raise the bit-line voltage when the sensing voltage is at a low level and close the pre-charge path when the sensing voltage is at a high level.
摘要翻译：提供记忆。存储器包括存储单元，钳位晶体管，反相器，位线，预充电路径以及检测器和控制器电路。存储器耦合到钳位晶体管。钳位晶体管具有第一端，第二端和控制端。逆变器具有电连接到钳位晶体管的第二端的输入端和电连接到钳位晶体管的控制端的输出端。位线电连接到钳位晶体管的第二端和反相器的输入端，并在其上具有位线电压。预充电路径通过其上具有感测电压的节点电连接到钳位晶体管的第一端。检测器和控制器电路电连接到钳位晶体管的第一端和用于检测感测电压的预充电路径，以便当感测电压为一个时，打开预充电路径以升高位线电压低电平并且当感测电压处于高电平时闭合预充电路径。

2. 发明授权

US07595682B2 Multi-stage charge pump without threshold drop with frequency modulation between embedded mode operations 有权
标题翻译：多级电荷泵，无嵌入式模式操作之间的频率调制门限下降
公开(公告)号：US07595682B2
公开(公告)日：2009-09-29
申请号：US11064920
申请日：2005-02-24
申请人： Yufe Feng Lin , Yu Shen Lin , Roger Chen , Chun Hsiung Hung
发明人： Yufe Feng Lin , Yu Shen Lin , Roger Chen , Chun Hsiung Hung
IPC分类号： G05F1/10
CPC分类号： H02M3/073 , H02M2003/075
摘要： A multimode charge pump circuit has a single charge pump that is responsive to a set of clock signals. The set of clock signals is provided in a first mode with a variable frequency according to a first function of the supply potential and temperature, and in a second mode with a variable frequency according to a second function of the supply potential and temperature. Circuitry configures all of the plurality of stages in series during the first mode in order to produce a higher voltage output, and configures a subset of the plurality of stages in series, while disabling the other stages, during the second mode in order to produce a lower voltage output. A precharge circuit is provided that operates as a supply node in the second mode, and as a precharge/clamp in the first mode.
摘要翻译：多模电荷泵电路具有响应于一组时钟信号的单个电荷泵。根据电源电位和温度的第一功能，在第一模式下以一个可变频率提供一组时钟信号，并且根据电源电位和温度的第二功能以第二种可变频率提供时钟信号。电路在第一模式期间配置串联的所有多个级，以便产生较高的电压输出，并且在第二模式期间在禁用其它级的同时，在多个级的串联中配置子集，以产生较低的电压输出。提供预充电电路，其在第二模式中作为供电节点工作，并且作为第一模式中的预充电/钳位。

3. 发明申请

US20090201747A1 MEMORY, BIT-LINE PRE-CHARGE CIRCUIT AND BIT-LINE PRE-CHARGE METHOD 有权
标题翻译：存储器，位线预充电电路和位线预充电方法
公开(公告)号：US20090201747A1
公开(公告)日：2009-08-13
申请号：US12027333
申请日：2008-02-07
申请人： Jer-Hau Hsu , Fu-Nian Liang , Yufe-Feng Lin
发明人： Jer-Hau Hsu , Fu-Nian Liang , Yufe-Feng Lin
IPC分类号： G11C7/00
CPC分类号： G11C7/12
摘要： A memory is provided. The memory includes a memory cell, a clamp transistor, an inverter, a bit line, a pre-charge path and a detector and controller circuit. The memory is coupled to the clamp transistor. The clamp transistor has a first end, a second end and a control end. The inverter has an input end electrically connected to the second end of the clamp transistor and an output end electrically connected to the control end of the clamp transistor. The bit line is electrically connected to the second end of the clamp transistor and the input end of the inverter and has a bit-line voltage thereon. The pre-charge path is electrically connected to the first end of the clamp transistor through a node having a sensing voltage thereon. The detector and controller circuit is electrically connected to the first end of the clamp transistor and the pre-charge path for detecting the sensing voltage in order to open the pre-charge path to raise the bit-line voltage when the sensing voltage is at a low level and close the pre-charge path when the sensing voltage is at a high level.
摘要翻译：提供记忆。存储器包括存储单元，钳位晶体管，反相器，位线，预充电路径以及检测器和控制器电路。存储器耦合到钳位晶体管。钳位晶体管具有第一端，第二端和控制端。逆变器具有电连接到钳位晶体管的第二端的输入端和电连接到钳位晶体管的控制端的输出端。位线电连接到钳位晶体管的第二端和反相器的输入端，并在其上具有位线电压。预充电路径通过其上具有感测电压的节点电连接到钳位晶体管的第一端。检测器和控制器电路电连接到钳位晶体管的第一端和用于检测感测电压的预充电路径，以便当感测电压为一个时，打开预充电路径以升高位线电压低电平并且当感测电压处于高电平时闭合预充电路径。

4. 发明授权

US08898439B2 Serial flash memory and address transmission method thereof 有权
标题翻译：串行闪存及其地址传输方法
公开(公告)号：US08898439B2
公开(公告)日：2014-11-25
申请号：US12837823
申请日：2010-07-16
申请人： Kuen-Long Chang , Yufe-Feng Lin , Chun-Hsiung Hung
发明人： Kuen-Long Chang , Yufe-Feng Lin , Chun-Hsiung Hung
IPC分类号： G06F9/34 , G11C7/10 , G06F9/30 , G06F9/38
CPC分类号： G11C7/10 , G06F9/30149 , G06F9/342 , G06F9/3875
摘要： A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock.
摘要翻译：串行闪存及其地址发送方法。串行闪速存储器根据第一地址长度选择性地寻址第一存储器空间，或者根据长于第一地址长度的第二地址长度寻址第二存储器空间。如果根据第一地址长度寻址第一存储器空间，则在地址持续时间内完全接收到第一存储器地址，从而从起始时钟开始输出与第一存储器地址对应的数据。在地址发送方法中，如果根据第二地址长度寻址第二存储器空间，则在地址持续时间内接收第二存储器地址的一部分。第二存储器地址的另一部分在等待时间段内被接收，使得对应于第二存储器地址的数据最初从起始时钟输出。

5. 发明申请

US20110016288A1 Serial Flash Memory and Address Transmission Method Thereof 有权
标题翻译：串行闪存及其地址传输方法
公开(公告)号：US20110016288A1
公开(公告)日：2011-01-20
申请号：US12837823
申请日：2010-07-16
申请人： Kuen-Long Chang , Yufe-Feng Lin , Chun-Hsiung Hung
发明人： Kuen-Long Chang , Yufe-Feng Lin , Chun-Hsiung Hung
IPC分类号： G06F12/06
CPC分类号： G11C7/10 , G06F9/30149 , G06F9/342 , G06F9/3875
摘要： A serial flash memory and an address transmission method thereof. The serial flash memory selectively addresses a first memory space according to a first address length or addresses a second memory space according to a second address length longer than the first address length. If the first memory space is addressed according to the first address length, a first memory address is completely received within an address time duration so that data corresponding to the first memory address is initially outputted from a starting clock. In the address transmission method, if the second memory space is addressed according to the second address length, a portion of a second memory address is received within the address time duration. The other portion of the second memory address is received within a waiting time duration so that data corresponding to the second memory address is initially outputted from the starting clock.
摘要翻译：串行闪存及其地址发送方法。串行闪速存储器根据第一地址长度选择性地寻址第一存储器空间，或者根据长于第一地址长度的第二地址长度寻址第二存储器空间。如果根据第一地址长度寻址第一存储器空间，则在地址持续时间内完全接收到第一存储器地址，从而从起始时钟开始输出与第一存储器地址对应的数据。在地址发送方法中，如果根据第二地址长度寻址第二存储器空间，则在地址持续时间内接收第二存储器地址的一部分。第二存储器地址的另一部分在等待时间段内被接收，使得对应于第二存储器地址的数据最初从起始时钟输出。

6. 发明授权

US07400536B1 Memory system and a voltage regulator 有权
标题翻译：内存系统和电压调节器
公开(公告)号：US07400536B1
公开(公告)日：2008-07-15
申请号：US11693712
申请日：2007-03-30
申请人： Yufe Feng Lin , Yi-Chun Shih , Kuen-Long Chang
发明人： Yufe Feng Lin , Yi-Chun Shih , Kuen-Long Chang
IPC分类号： G11C11/34
CPC分类号： G11C5/147
摘要： A regulator for regulating a program voltage of a memory device is introduced. The regulator includes an operating amplifier, a program path emulation apparatus, and a current mirror coupled to the program path emulation apparatus and the operating amplifier. The current mirror is for controlling a current flowing in the program path emulation apparatus a multiple of a predetermined current. The program path emulation apparatus includes a bit line selection emulation unit for emulating a bit line selecting unit of the memory device, a path resistor for emulating a program path of a memory cell of the memory device, and a sector selection emulation unit for emulating a sector selecting unit of the memory device. The value of the predetermined current may be varied according to the program times of the memory cells of the memory device.
摘要翻译：引入了用于调节存储器件的编程电压的调节器。调节器包括运算放大器，程序路径仿真装置和耦合到程序路径仿真装置和运算放大器的电流镜。电流镜用于控制在程序路径仿真装置中流过预定电流倍数的电流。程序路径仿真装置包括用于仿真存储器件的位线选择单元的位线选择仿真单元，用于仿真存储器件的存储单元的程序路径的路径电阻器和用于模拟存储器件的扇区选择仿真单元存储器件的扇区选择单元。预定电流的值可以根据存储器件的存储器单元的编程时间而改变。

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