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1. 发明申请

US20090250818A1 VIA ELECTROMIGRATION IMPROVEMENT BY CHANGING THE VIA BOTTOM GEOMETRIC PROFILE 有权
标题翻译：通过改变通过底部几何轮廓的电力改进
公开(公告)号：US20090250818A1
公开(公告)日：2009-10-08
申请号：US12486521
申请日：2009-06-17
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L23/522
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

2. 发明授权

US07781895B2 Via electromigration improvement by changing the via bottom geometric profile 有权
公开(公告)号：US07781895B2
公开(公告)日：2010-08-24
申请号：US12486521
申请日：2009-06-17
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

3. 发明授权

US07691739B2 Via electromigration improvement by changing the via bottom geometric profile 有权
标题翻译：通过改变通孔底部几何轮廓来改善电迁移
公开(公告)号：US07691739B2
公开(公告)日：2010-04-06
申请号：US11374848
申请日：2006-03-13
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

4. 发明授权

US07045455B2 Via electromigration improvement by changing the via bottom geometric profile 有权
标题翻译：通过改变通孔底部几何轮廓来改善电迁移
公开(公告)号：US07045455B2
公开(公告)日：2006-05-16
申请号：US10692028
申请日：2003-10-23
申请人： Beichao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Beichao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

5. 发明授权

US11202600B2 Multifunctional neurophysiologic monitoring and probing system and a method of implementing the same 有权
公开(公告)号：US11202600B2
公开(公告)日：2021-12-21
申请号：US16088449
申请日：2017-09-04
申请人： Qiang Guo , Zhengwei Guo , Junying Feng
发明人： Qiang Guo , Zhengwei Guo , Junying Feng
IPC分类号： A61B5/00
摘要： A multifunctional neurophysiologic monitoring and probing system, having a main unit (1), a main wire (2), negative electrode neurophysiologic monitoring and probing parts and positive electrode neurophysiologic monitoring and probing parts; one end of the main wire (2) is connected with the main unit (1); another end of the main wire is divided into two branch wires connecting with the negative electrode neurophysiologic monitoring and probing parts and the positive electrode neurophysiologic monitoring and probing parts respectively.

6. 发明授权

US09981284B2 Method of forming a laminate 有权
公开(公告)号：US09981284B2
公开(公告)日：2018-05-29
申请号：US13728262
申请日：2012-12-27
申请人： Qiang Guo , Guoliang Pan , Lianxiang Wang , Xiaoye Liu
发明人： Qiang Guo , Guoliang Pan , Lianxiang Wang , Xiaoye Liu
IPC分类号： B05D1/06 , B05D3/00 , C23C4/00 , F16C33/00 , B05D5/08 , F16C33/20 , B05D7/00 , B05D3/02
CPC分类号： B05D1/06 , B05D3/0218 , B05D5/083 , B05D7/54 , B05D2202/00 , B05D2350/65 , B05D2451/00 , F16C33/206 , F16C33/208 , F16C2202/10 , F16C2208/32 , F16C2208/36 , F16C2223/42 , F16C2223/80 , F16C2240/48 , F16C2240/54 , F16C2240/60 , Y10T428/12049 , Y10T428/12472 , Y10T428/12549 , B05D2401/32
摘要： A bearing article can include a metal substrate having a bronze layer; a PEEK layer; a PTFE composition layer overlying and penetrating the PEEK layer. A method for preparing a bearing article can include providing a metal substrate with a sintered bronze layer, electrostatic spraying a non-fluorinated polymer onto the metal substrate followed by spraying a fluorinated polymer onto the non-fluorinated polymer and heat rolling to form a laminate.

7. 发明授权

US08452905B2 Serial port remote control circuit 失效
标题翻译：串口遥控电路
公开(公告)号：US08452905B2
公开(公告)日：2013-05-28
申请号：US13081522
申请日：2011-04-07
申请人： Qiang Guo , Min Tan
发明人： Qiang Guo , Min Tan
IPC分类号： G06F13/12 , G06F13/38
CPC分类号： G06F13/385 , G05B19/0423 , G05B2219/25171
摘要： A serial port remote control circuit includes a first interface circuit, a control circuit, an output circuit, and a power circuit. The first interface circuit converts recommended standard 232 (RS232) level signals to transistor-transistor logic (TTL) level signals or vice versa. The control circuit is connected to the first interface circuit, to convert the TTL level signals to physical bus signal or vice versa. The output circuit is connected to the control circuit, to convert the received physical bus signals from the control circuit to network bus signals or vice versa. The power circuit outputs a first voltage and a second voltage converted from the first voltage to the control circuit, the first interface circuit, and the output circuit.
摘要翻译：串行端口遥控电路包括第一接口电路，控制电路，输出电路和电源电路。第一个接口电路将推荐的标准232（RS232）电平信号转换为晶体管晶体管逻辑（TTL）电平信号，反之亦然。控制电路连接到第一接口电路，将TTL电平信号转换为物理总线信号，反之亦然。输出电路连接到控制电路，将接收的物理总线信号从控制电路转换为网络总线信号，反之亦然。电源电路将从第一电压转换的第一电压和第二电压输出到控制电路，第一接口电路和输出电路。

8. 发明申请

US20130128762A1 METHOD AND APPARATUS FOR CONTROLLING INTELLIGENT ANTENNA SYSTEM 有权
标题翻译：用于控制智能天线系统的方法和装置
公开(公告)号：US20130128762A1
公开(公告)日：2013-05-23
申请号：US13812456
申请日：2011-07-27
申请人： Qiang Guo
发明人： Qiang Guo
IPC分类号： H04W52/24
CPC分类号： H04W52/241 , H04B7/0602 , H04B7/061 , H04B7/0691 , H04W52/20 , H04W52/42
摘要： A method and an apparatus for controlling an intelligent antenna system are provided. The method includes: pre-configuring a Request Min Rate (RR), a Request Max PER (RP) and a request TX power (RTP); A). determining a current antenna configuration and a current transmitting power of the intelligent antenna system; B). reducing the transmitting power as long as the packet loss ratio does not exceed the RP with the current antenna configuration and with RR as a current transmitting rate, and adopting a reduced transmitting power as the current transmitting power; and C). switching between different antenna configurations at intervals with the current transmitting rate and the current transmitting power to obtain an antenna configuration under which the packet loss ratio is lower than the current packet loss ratio, and performing B).
摘要翻译：提供了一种用于控制智能天线系统的方法和装置。该方法包括：预配置请求最小速率（RR），请求最大PER（RP）和请求TX功率（RTP）; 一个）。确定智能天线系统的当前天线配置和当前发射功率; B）。只要分组丢失率不超过当前天线配置的RP和RR作为当前传输速率，并采用降低的发射功率作为当前发射功率，则降低发射功率; 和C）。以当前传输速率和当前发射功率间隔切换不同天线配置，以获得丢包率低于当前分组丢失率的天线配置，并执行B）。

9. 发明申请

US20060160354A1 Via electromigration improvement by changing the via bottom geometric profile 有权
公开(公告)号：US20060160354A1
公开(公告)日：2006-07-20
申请号：US11374848
申请日：2006-03-14
申请人： BeiChao Zhang , Chun Low , Hong Lee , Sang Loong , Qiang Guo
发明人： BeiChao Zhang , Chun Low , Hong Lee , Sang Loong , Qiang Guo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

10. 发明授权

US07061966B2 Frame synchronization and scrambling code indentification in wireless communications systems and methods therefor 有权
标题翻译：无线通信系统中的帧同步和扰码识别及其方法
公开(公告)号：US07061966B2
公开(公告)日：2006-06-13
申请号：US10376191
申请日：2003-02-27
申请人： Brian Storm , Qiang Guo , Ming D. Tan , Xuping Zhou , Mang Zhu
发明人： Brian Storm , Qiang Guo , Ming D. Tan , Xuping Zhou , Mang Zhu
IPC分类号： H04L27/30
CPC分类号： H04B1/70735
摘要： A mobile wireless communications device and methods therefore, including receiving a signal (710), storing a portion of the received signal (730), identifying all possible pilot signals by determining slot boundary information for the stored signal portion (720), determining frame boundary information and/or scrambling code information (760) of the stored signal portion by correlating the stored signal portion with the scrambling codes based on the slot boundary information. In other embodiments, the search is performed in real-time without storing the signal.
摘要翻译：因此，移动无线通信设备和方法包括接收信号（710），存储接收信号的一部分（730），通过确定所存储的信号部分（720）的时隙边界信息来识别所有可能的导频信号，确定帧边界信息和/或加扰码信息（760），通过将存储的信号部分与基于时隙边界信息的扰码相关联。在其他实施例中，搜索是实时执行的，而不存储信号。

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