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1. 发明授权

US06350661B2 Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts 失效
标题翻译：氮化硅封装的浅沟槽隔离方法，用于制造具有无边界接触的亚微米器件
公开(公告)号：US06350661B2
公开(公告)日：2002-02-26
申请号：US09882682
申请日：2001-06-18
申请人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76897
摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.
摘要翻译：具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽盖层。氮化硅钝化沟槽帽用于形成无边界或“非成形”的电触头，而不会减少聚对多晶间距。形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。在接触孔打开期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅沟槽覆盖层保持完好，保护沟槽区域边缘处的P-N结。防止导电钨金属插塞的后续处理被钝化沟槽盖短路。这种在部分凹陷的沟槽隔离方案中与钝化沟槽盖形成无边界接触的方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。此外，在随后的清洁工艺步骤中，使用氮化硅沟槽帽保护下面的STI沟槽氧化物。此外，除了最小化晶体管结漏电外，氮化物盖还可保护STI氧化物免于过度的凹陷形成，并防止STI接缝的暴露。

2. 发明授权

US06297126B1 Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts 失效
标题翻译：氮化硅封装的浅沟槽隔离方法，用于制造具有无边界接触的亚微米器件
公开(公告)号：US06297126B1
公开(公告)日：2001-10-02
申请号：US09351240
申请日：1999-07-12
申请人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76897
摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.
摘要翻译：具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽盖层。氮化硅钝化沟槽帽用于形成无边界或“非成形”的电触头，而不会减少聚对多晶间距。形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。在接触孔打开期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅沟槽覆盖层保持完好，保护沟槽区域边缘处的P-N结。防止导电钨金属插塞的后续处理被钝化沟槽盖短路。这种在部分凹陷的沟槽隔离方案中与钝化沟槽盖形成无边界接触的方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。此外，在随后的清洁工艺步骤中，使用氮化硅沟槽帽保护下面的STI沟槽氧化物。此外，除了最小化晶体管结漏电外，氮化物盖还可保护STI氧化物免于过度的凹陷形成，并防止STI接缝的暴露。

3. 发明授权

US06228727B1 Method to form shallow trench isolations with rounded corners and reduced trench oxide recess 有权
标题翻译：形成具有圆角和减少的沟槽氧化物凹陷的浅沟槽隔离的方法
公开(公告)号：US06228727B1
公开(公告)日：2001-05-08
申请号：US09405061
申请日：1999-09-27
申请人： Chong Wee Lim , Soh Yun Siah , Eng Hua Lim , Kong-Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Soh Yun Siah , Eng Hua Lim , Kong-Hean Lee , Chun Hui Low
IPC分类号： H01L21336
CPC分类号： H01L21/3086 , H01L21/31053 , H01L21/31612 , H01L21/32 , H01L21/76232
摘要： A method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited. The silicon nitride layer and the pad oxide layer are patterned to form a hard mask. The openings in the hard mask correspond to planned trenches in the semiconductor substrate. A silicon dioxide layer is deposited overlying the silicon nitride layer and the semiconductor substrate. The silicon dioxide layer is anisotropically etched to form sidewall spacers on the inside of the openings of the hard mask. The semiconductor substrate is etched to form the trenches. The sidewall spacers are etched away. The semiconductor substrate is sputter etched to round the corners of the trenches. An oxide trench lining layer is grown overlying the semiconductor substrate. A trench fill layer is deposited overlying the silicon nitride layer and filling the trenches. The trench fill layer is polished down to the top surface of the silicon nitride layer. The silicon nitride layer is etched away. The trench fill layer and the pad oxide layer are polished down to the top surface of the semiconductor substrate to complete the shallow trench isolation, and the integrated circuit device is completed.
摘要翻译：已经实现了制造浅沟槽隔离的方法。提供半导体衬底。生长覆盖半导体衬底的焊盘氧化物层。沉积氮化硅层。将氮化硅层和焊盘氧化物层图案化以形成硬掩模。硬掩模中的开口对应于半导体衬底中的规划沟槽。沉积氮化硅层和半导体衬底上的二氧化硅层。二氧化硅层被各向异性地蚀刻以在硬掩模的开口的内侧上形成侧壁间隔物。蚀刻半导体衬底以形成沟槽。蚀刻掉侧壁间隔物。对半导体衬底进行溅射蚀刻以使沟槽的角落四周。生长在半导体衬底上的氧化物沟槽衬里层。沉积氮化硅层并填充沟槽的沟槽填充层。沟槽填充层被抛光到氮化硅层的顶表面。蚀刻掉氮化硅层。沟槽填充层和焊盘氧化物层被抛光到半导体衬底的顶表面以完成浅沟槽隔离，并且集成电路器件完成。

4. 发明授权

US06265302B1 Partially recessed shallow trench isolation method for fabricating borderless contacts 有权
标题翻译：用于制造无边界触点的部分凹槽浅沟槽隔离方法
公开(公告)号：US06265302B1
公开(公告)日：2001-07-24
申请号：US09351238
申请日：1999-07-12
申请人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
IPC分类号： H01L214763
CPC分类号： H01L21/76897 , H01L21/76232
摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench liner of silicon nitride. The silicon nitride passivating liner is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride liner remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench liner. This method of forming borderless contacts with a passivating trench liner in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. In addition, the use of this invention's semi-recessed STI process scheme helps to reduce the aspect ratio of the trench, thereby aiding the filling of the trench. Therefore, with the process described herein, STI oxide seam formation is eliminated.
摘要翻译：具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽衬垫。氮化硅钝化衬垫用于形成无边界或“非成形”电触头，而不会减少聚对多晶间距。形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。在接触孔开口期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅衬垫保持完好，保护沟槽区域边缘处的P-N结。防止导电钨金属插塞的后续处理被钝化沟槽衬垫短路。这种在部分凹槽沟槽隔离方案中与钝化沟槽衬垫形成无边界接触的这种方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。此外，使用本发明的半凹陷STI工艺方案有助于减小沟槽的纵横比，从而有助于填充沟槽。因此，通过本文所述的方法，消除了STI氧化物接缝形成。

5. 发明授权

US6165871A Method of making low-leakage architecture for sub-0.18 .mu.m salicided CMOS device 失效
标题翻译：亚0.18微米水银CMOS器件制造低泄漏架构的方法
公开(公告)号：US6165871A
公开(公告)日：2000-12-26
申请号：US356003
申请日：1999-07-16
申请人： Eng Hua Lim , Chong Wee Lim , Soh Yun Siah , Kong Hean Lee , Pei Ching Lee
发明人： Eng Hua Lim , Chong Wee Lim , Soh Yun Siah , Kong Hean Lee , Pei Ching Lee
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8234
CPC分类号： H01L29/665 , H01L21/76232 , H01L21/823481
摘要： A method for forming a stepped shallow trench isolation is described. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited overlying the pad oxide layer. The first nitride layer is etched through where it is not covered by a mask to provide an opening to the pad oxide layer. A first trench is etched through the pad oxide layer within the opening and into the semiconductor substrate. A second nitride layer is deposited overlying the first nitride layer and filling the first trench. Simultaneously, the second nitride layer is anisotropically etched to form nitride spacers on the sidewalls of the first trench and the semiconductor substrate is etched into where it is not covered by the spacers to form a second trench. Ions are implanted into the semiconductor substrate underlying the second trench. The first and second trenches are filled with an oxide layer. Thereafter, the first nitride and pad oxide layers are removed completing the formation of shallow trench isolation in the fabrication of an integrated circuit device. This nitride spacer STI architecture prevents STI corner oxide recess and enables borderless contact formation. This unique process reduces junction leakage and also reduces contact leakage.
摘要翻译：描述了形成阶梯式浅沟槽隔离的方法。衬垫氧化物层沉积在半导体衬底的表面上。沉积在衬垫氧化物层上的第一氮化物层。蚀刻第一氮化物层，其中未被掩模覆盖，以提供衬垫氧化物层的开口。通过开口内的衬垫氧化物层蚀刻第一沟槽并进入半导体衬底。沉积第二氮化物层，覆盖第一氮化物层并填充第一沟槽。同时，第二氮化物层被各向异性蚀刻以在第一沟槽的侧壁上形成氮化物间隔物，并且半导体衬底被蚀刻到不被间隔物覆盖的区域中以形成第二沟槽。离子被注入到第二沟槽下面的半导体衬底中。第一和第二沟槽填充有氧化物层。此后，去除在制造集成电路器件时完成形成浅沟槽隔离的第一氮化物层和衬垫氧化物层。该氮化物间隔物STI结构防止了STI拐角氧化物凹陷并且实现无边界接触形成。这种独特的工艺可减少结漏电流并减少接触泄漏。

6. 发明授权

US06271133B1 Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabrication 失效
标题翻译：用于浅结深亚微米器件制造的优化Co / Ti-自对准方案
公开(公告)号：US06271133B1
公开(公告)日：2001-08-07
申请号：US09290918
申请日：1999-04-12
申请人： Chong Wee Lim , Eng Hua Lim , Kin Leong Pey , Soh Yun Siah , Chun Hui Low
发明人： Chong Wee Lim , Eng Hua Lim , Kin Leong Pey , Soh Yun Siah , Chun Hui Low
IPC分类号： H01L2144
CPC分类号： H01L29/66507 , H01L21/28518 , H01L29/665 , H01L29/66545 , Y10S438/97
摘要： A new method is established to form different silicide layers over the top of the gate electrode and the surface of the source/drain regions. A thin layer of TiSi2 is formed over the source/drain regions by depositing a layer of titanium and annealing this layer with the silicon substrate. The gate electrode is created as a recessed electrode, in the top recession of the electrode a layer of CoSi2 is formed by depositing a layer of cobalt over the gate electrode. This layer of COSi2 serves as the electrical gate contact point.
摘要翻译：建立了一种新的方法，以在栅电极的顶部和源极/漏极区的表面上形成不同的硅化物层。通过沉积钛层并用硅衬底退火该层，在源极/漏极区域上形成薄的TiSi 2层。栅电极被形成为凹陷电极，在电极的顶部凹陷中，通过在栅电极上沉积钴层形成CoSi 2层。该COSi2层用作电接触点。

7. 发明授权

US6093628A Ultra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS application 有权
标题翻译：用于深亚微米CMOS应用的超低电阻金属/多晶硅栅极
公开(公告)号：US6093628A
公开(公告)日：2000-07-25
申请号：US165003
申请日：1998-10-01
申请人： Chong Wee Lim , Kin Leong Pey , Soh Yun Siah , Eng Hwa Lim , Lap Chan
发明人： Chong Wee Lim , Kin Leong Pey , Soh Yun Siah , Eng Hwa Lim , Lap Chan
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8238 , H01L29/49 , H01L21/4763 , H01L21/3205 , H01L21/44
CPC分类号： H01L29/6659 , H01L21/28061 , H01L21/823842 , H01L29/4941 , H01L29/66545
摘要： A method for fabricating a deep sub-micron gate electrode, comprising polysilicon and metal, having ultra-low sheet resistance. The process begins by forming shallow trench isolation regions 14 in a silicon substrate 10. A gate oxide layer is formed on device areas. A doped blanket polysilicon layer 16 is formed on the gate oxide layer. A cap layer 20 composed of silicon nitride is formed on the polysilicon layer 16. The cap layer 20 and the polysilicon layer 16 are patterned by photoresist masking and anisotropic etching to form a bottom gate electrode 16A and a gate cap 20A. Lightly doped source/drain areas 22 are formed adjacent to the gate bottom electrodes 16A by ion implantation. Sidewall spacers 21 are formed on the gate electrode 16A and gate cap 20A. Source/drain regions 24 are formed by ion implantation adjacent to said sidewall spacers 21. A metal silicide 23 is formed on the source/drain regions 24. An interlevel dielectric layer (ILD) 28 is deposited and planarized by CMP using the gate cap 20A as a CMP stop. The gate cap 20 is selectively removed. A barrier layer 32 composed of a TaN, CoWP, TiN or W.sub.x N.sub.y is formed over the planarized IDL 28A. A top gate layer 36 composed of copper or tungsten is formed on the barrier layer 32. The top gate layer 36 and the barrier layer 32 are removed down to the level of the top of the ILD 28 using CMP; thereby forming a top gate electrode. A passivation layer 40, composed of Pd or NiP is selectively deposited over the gate top electrode 36A.
摘要翻译：一种制造具有超薄薄层电阻的深亚微米栅电极的方法，包括多晶硅和金属。该过程通过在硅衬底10中形成浅沟槽隔离区14开始。栅极氧化物层形成在器件区域上。掺杂的覆盖多晶硅层16形成在栅极氧化物层上。在多晶硅层16上形成由氮化硅构成的覆盖层20.通过光致抗蚀剂掩模和各向异性蚀刻对覆盖层20和多晶硅层16进行构图以形成底栅电极16A和栅极帽20A。通过离子注入，与栅极底部电极16A相邻地形成轻掺杂源极/漏极区域22。侧壁间隔件21形成在栅极16A和栅极盖20A上。源极/漏极区24通过与所述侧壁间隔物21相邻的离子注入而形成。金属硅化物23形成在源/漏区24上。层间绝缘层（ILD）28通过CMP使用栅极帽20A沉积并平坦化作为CMP停止。选择性地去除栅极盖20。在平坦化的IDL28A上形成由TaN，CoWP，TiN或WxNy构成的阻挡层32。在势垒层32上形成由铜或钨构成的顶栅层36.顶栅层36和势垒层32使用CMP向下移至ILD28顶部的电平; 从而形成顶栅电极。由栅极顶电极36A选择性地沉积由Pd或NiP组成的钝化层40。

8. 发明授权

US06846359B2 Epitaxial CoSi2 on MOS devices 失效
标题翻译：外延CoSi2在MOS器件上
公开(公告)号：US06846359B2
公开(公告)日：2005-01-25
申请号：US10280668
申请日：2002-10-25
申请人： Chong Wee Lim , Chan Soo Shin , Ivan Georgiev Petrov , Joseph E. Greene
发明人： Chong Wee Lim , Chan Soo Shin , Ivan Georgiev Petrov , Joseph E. Greene
IPC分类号： C30B1/00 , C30B25/02 , G30B25/04
CPC分类号： C30B1/00 , C30B25/02 , C30B29/10
摘要： An SixNy or SiOxNy liner is formed on a MOS device. Cobalt is then deposited and reacts to form an epitaxial CoSi2 layer underneath the liner. The CoSi2 layer may be formed through a solid phase epitaxy or reactive deposition epitaxy salicide process. In addition to high quality epitaxial CoSi2 layers, the liner formed during the invention can protect device portions during etching processes used to form device contacts. The liner can act as an etch stop layer to prevent excessive removal of the shallow trench isolation, and protect against excessive loss of the CoSi2 layer.
摘要翻译：在MOS器件上形成SixNy或SiOxNy衬垫。然后沉积钴并且反应以在衬垫下方形成外延CoSi 2层。可以通过固相外延或反应性沉积外延自对准硅化物工艺形成CoSi 2层。除了高质量的外延CoSi2层之外，本发明中形成的衬垫还可以在用于形成器件触点的蚀刻工艺期间保护器件部分。衬里可以用作蚀刻停止层，以防止浅沟槽隔离物的过度去除，并且防止CoSi2层的过度损耗。

9. 发明授权

US06762131B2 Method for large-scale fabrication of atomic-scale structures on material surfaces using surface vacancies 失效
标题翻译：使用表面空位在材料表面上大规模地制造原子尺度结构的方法
公开(公告)号：US06762131B2
公开(公告)日：2004-07-13
申请号：US10123031
申请日：2002-04-13
申请人： Chong Wee Lim , Kenji Ohmori , Ivan Georgiev Petrov , Joseph E. Greene
发明人： Chong Wee Lim , Kenji Ohmori , Ivan Georgiev Petrov , Joseph E. Greene
IPC分类号： H01L21302
CPC分类号： H01L21/306 , C30B25/18 , H01L21/02381 , H01L21/0243 , H01L21/02658 , H01L21/28525 , H01L21/28568
摘要： A method for forming atomic-scale structures on a surface of a substrate on a large-scale includes creating a predetermined amount of surface vacancies on the surface of the substrate by removing an amount of atoms on the surface of the material corresponding to the predetermined amount of the surface vacancies. Once the surface vacancies have been created, atoms of a desired structure material are deposited on the surface of the substrate to enable the surface vacancies and the atoms of the structure material to interact. The interaction causes the atoms of the structure material to form the atomic-scale structures.
摘要翻译：大规模地在基板表面上形成原子级结构的方法包括：通过去除对应于预定量的材料表面上的原子数量来在基板的表面上产生预定量的表面空位的表面空缺。一旦形成表面空位，所需结构材料的原子沉积在衬底的表面上，以使表面空位和结构材料的原子相互作用。相互作用导致结构材料的原子形成原子尺度结构。

10. 发明授权

US06797598B2 Method for forming an epitaxial cobalt silicide layer on MOS devices 失效
标题翻译：在MOS器件上形成外延钴硅化物层的方法
公开(公告)号：US06797598B2
公开(公告)日：2004-09-28
申请号：US10226101
申请日：2002-08-22
申请人： Chong Wee Lim , Chan Soo Shin , Daniel Gall , Ivan Georgiev Petrov , Joseph E. Greene
发明人： Chong Wee Lim , Chan Soo Shin , Daniel Gall , Ivan Georgiev Petrov , Joseph E. Greene
IPC分类号： H01L213205
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/28518 , H01L29/665
摘要： A method for forming an epitaxial cobalt silicide layer on a MOS device includes sputter depositing cobalt in an ambient to form a first layer of cobalt suicide on a gate and source/drain regions of the MOS device. Subsequently, cobalt is sputter deposited again in an ambient of argon to increase the thickness of the cobalt silicide layer to a second thickness.
摘要翻译：在MOS器件上形成外延钴硅化物层的方法包括在环境中溅射沉积钴以在MOS器件的栅极和源极/漏极区上形成第一层硅化钴。随后，再次在氩气环境中溅射沉积钴，以将硅化钴层的厚度增加到第二厚度。

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