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1. 发明申请

US20130256834A1 BACK-SIDE MOM/MIM DEVICES 有权
标题翻译：背面MOM / MIM设备
公开(公告)号：US20130256834A1
公开(公告)日：2013-10-03
申请号：US13430778
申请日：2012-03-27
申请人： Juan Boon TAN , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah , Shunqiang Gong
发明人： Juan Boon TAN , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah , Shunqiang Gong
IPC分类号： H01L29/02 , H01L21/02
CPC分类号： H01L23/5223 , H01L23/481 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Back-side MOM/MIM structures are integrated on a device with front-side circuitry. Embodiments include forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; and forming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate. Other embodiments include forming a through-silicon via (TSV), in the substrate, connecting the MOM capacitor, the MIM capacitor, or a combination thereof to the circuitry on the front side of the substrate.
摘要翻译：背面MOM / MIM结构集成在具有前端电路的设备上。实施例包括形成具有与前侧相对的前侧和后侧的基板，所述基板在基板的正面上包括电路; 以及在衬底的背面上形成金属 - 氧化物 - 金属（MOM）电容器，金属 - 绝缘体 - 金属（MIM）电容器或其组合。其他实施例包括在衬底中形成穿硅通孔（TSV），将MOM电容器，MIM电容器或其组合连接到衬底前侧上的电路。

2. 发明授权

US06586314B1 Method of forming shallow trench isolation regions with improved corner rounding 失效
标题翻译：形成浅沟槽隔离区域的方法具有改进的拐角圆角
公开(公告)号：US06586314B1
公开(公告)日：2003-07-01
申请号：US10266952
申请日：2002-10-08
申请人： Soh Yun Siah , Liang Choo Hsia , Jia Zhen Zheng , Chew Hoe Ang
发明人： Soh Yun Siah , Liang Choo Hsia , Jia Zhen Zheng , Chew Hoe Ang
IPC分类号： H01L2176
CPC分类号： H01L21/76235
摘要： A method of forming a shallow trench isolation (STI), region in a semiconductor substrate featuring a process sequence that results in desired rounded corners for the sides of active device regions located butting the STI region, has been developed. The process sequence features formation of, followed by removal of, a silicon dioxide layer which was thermally grown in a top portion of the semiconductor substrate, wherein the top portion of semiconductor was subjected to an ion implantation procedure prior to the oxidation procedure. The above process sequence results in a recessed portion of semiconductor located adjacent to unoxidized portions of semiconductor which underlay an oxidation resistant shape, and feature rounded corners. Insulator spacers are then formed on the sides of the oxidation resistant shape, overlying and protecting the rounded comers of subsequent active device regions from a dry etch procedure used to selectively define a shallow trench shape in the exposed semiconductor region. Insulator filling and planarization procedures result in the formation of an STI region, located adjacent to active device regions which feature the desired rounded corners.
摘要翻译：已经开发了在半导体衬底中形成浅沟槽隔离（STI）区域的方法，该半导体衬底的特征在于产生针对STI区域的有源器件区域的侧面的期望的圆角的工艺序列。处理顺序特征在于形成，随后除去在半导体衬底的顶部热生长的二氧化硅层，其中半导体的顶部在氧化过程之前进行离子注入工艺。上述处理顺序导致位于半导体的未氧化部分附近的半导体的凹陷部分，其具有抗氧化的形状，并且具有圆角。然后在耐氧化形状的侧面上形成绝缘体间隔物，覆盖并保护随后的有源器件区域的圆角从用于在暴露的半导体区域中选择性地限定浅沟槽形状的干蚀刻工艺。绝缘体填充和平坦化程序导致STI区域的形成，其位于具有所需圆角的有源器件区域附近。

3. 发明授权

US06297126B1 Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts 失效
标题翻译：氮化硅封装的浅沟槽隔离方法，用于制造具有无边界接触的亚微米器件
公开(公告)号：US06297126B1
公开(公告)日：2001-10-02
申请号：US09351240
申请日：1999-07-12
申请人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76897
摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.
摘要翻译：具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽盖层。氮化硅钝化沟槽帽用于形成无边界或“非成形”的电触头，而不会减少聚对多晶间距。形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。在接触孔打开期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅沟槽覆盖层保持完好，保护沟槽区域边缘处的P-N结。防止导电钨金属插塞的后续处理被钝化沟槽盖短路。这种在部分凹陷的沟槽隔离方案中与钝化沟槽盖形成无边界接触的方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。此外，在随后的清洁工艺步骤中，使用氮化硅沟槽帽保护下面的STI沟槽氧化物。此外，除了最小化晶体管结漏电外，氮化物盖还可保护STI氧化物免于过度的凹陷形成，并防止STI接缝的暴露。

4. 发明授权

US06228727B1 Method to form shallow trench isolations with rounded corners and reduced trench oxide recess 有权
标题翻译：形成具有圆角和减少的沟槽氧化物凹陷的浅沟槽隔离的方法
公开(公告)号：US06228727B1
公开(公告)日：2001-05-08
申请号：US09405061
申请日：1999-09-27
申请人： Chong Wee Lim , Soh Yun Siah , Eng Hua Lim , Kong-Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Soh Yun Siah , Eng Hua Lim , Kong-Hean Lee , Chun Hui Low
IPC分类号： H01L21336
CPC分类号： H01L21/3086 , H01L21/31053 , H01L21/31612 , H01L21/32 , H01L21/76232
摘要： A method of fabricating shallow trench isolations has been achieved. A semiconductor substrate is provided. A pad oxide layer is grown overlying the semiconductor substrate. A silicon nitride layer is deposited. The silicon nitride layer and the pad oxide layer are patterned to form a hard mask. The openings in the hard mask correspond to planned trenches in the semiconductor substrate. A silicon dioxide layer is deposited overlying the silicon nitride layer and the semiconductor substrate. The silicon dioxide layer is anisotropically etched to form sidewall spacers on the inside of the openings of the hard mask. The semiconductor substrate is etched to form the trenches. The sidewall spacers are etched away. The semiconductor substrate is sputter etched to round the corners of the trenches. An oxide trench lining layer is grown overlying the semiconductor substrate. A trench fill layer is deposited overlying the silicon nitride layer and filling the trenches. The trench fill layer is polished down to the top surface of the silicon nitride layer. The silicon nitride layer is etched away. The trench fill layer and the pad oxide layer are polished down to the top surface of the semiconductor substrate to complete the shallow trench isolation, and the integrated circuit device is completed.
摘要翻译：已经实现了制造浅沟槽隔离的方法。提供半导体衬底。生长覆盖半导体衬底的焊盘氧化物层。沉积氮化硅层。将氮化硅层和焊盘氧化物层图案化以形成硬掩模。硬掩模中的开口对应于半导体衬底中的规划沟槽。沉积氮化硅层和半导体衬底上的二氧化硅层。二氧化硅层被各向异性地蚀刻以在硬掩模的开口的内侧上形成侧壁间隔物。蚀刻半导体衬底以形成沟槽。蚀刻掉侧壁间隔物。对半导体衬底进行溅射蚀刻以使沟槽的角落四周。生长在半导体衬底上的氧化物沟槽衬里层。沉积氮化硅层并填充沟槽的沟槽填充层。沟槽填充层被抛光到氮化硅层的顶表面。蚀刻掉氮化硅层。沟槽填充层和焊盘氧化物层被抛光到半导体衬底的顶表面以完成浅沟槽隔离，并且集成电路器件完成。

5. 发明授权

US6165871A Method of making low-leakage architecture for sub-0.18 .mu.m salicided CMOS device 失效
标题翻译：亚0.18微米水银CMOS器件制造低泄漏架构的方法
公开(公告)号：US6165871A
公开(公告)日：2000-12-26
申请号：US356003
申请日：1999-07-16
申请人： Eng Hua Lim , Chong Wee Lim , Soh Yun Siah , Kong Hean Lee , Pei Ching Lee
发明人： Eng Hua Lim , Chong Wee Lim , Soh Yun Siah , Kong Hean Lee , Pei Ching Lee
IPC分类号： H01L21/336 , H01L21/762 , H01L21/8234
CPC分类号： H01L29/665 , H01L21/76232 , H01L21/823481
摘要： A method for forming a stepped shallow trench isolation is described. A pad oxide layer is deposited on the surface of a semiconductor substrate. A first nitride layer is deposited overlying the pad oxide layer. The first nitride layer is etched through where it is not covered by a mask to provide an opening to the pad oxide layer. A first trench is etched through the pad oxide layer within the opening and into the semiconductor substrate. A second nitride layer is deposited overlying the first nitride layer and filling the first trench. Simultaneously, the second nitride layer is anisotropically etched to form nitride spacers on the sidewalls of the first trench and the semiconductor substrate is etched into where it is not covered by the spacers to form a second trench. Ions are implanted into the semiconductor substrate underlying the second trench. The first and second trenches are filled with an oxide layer. Thereafter, the first nitride and pad oxide layers are removed completing the formation of shallow trench isolation in the fabrication of an integrated circuit device. This nitride spacer STI architecture prevents STI corner oxide recess and enables borderless contact formation. This unique process reduces junction leakage and also reduces contact leakage.
摘要翻译：描述了形成阶梯式浅沟槽隔离的方法。衬垫氧化物层沉积在半导体衬底的表面上。沉积在衬垫氧化物层上的第一氮化物层。蚀刻第一氮化物层，其中未被掩模覆盖，以提供衬垫氧化物层的开口。通过开口内的衬垫氧化物层蚀刻第一沟槽并进入半导体衬底。沉积第二氮化物层，覆盖第一氮化物层并填充第一沟槽。同时，第二氮化物层被各向异性蚀刻以在第一沟槽的侧壁上形成氮化物间隔物，并且半导体衬底被蚀刻到不被间隔物覆盖的区域中以形成第二沟槽。离子被注入到第二沟槽下面的半导体衬底中。第一和第二沟槽填充有氧化物层。此后，去除在制造集成电路器件时完成形成浅沟槽隔离的第一氮化物层和衬垫氧化物层。该氮化物间隔物STI结构防止了STI拐角氧化物凹陷并且实现无边界接触形成。这种独特的工艺可减少结漏电流并减少接触泄漏。

6. 发明申请

US20130149851A1 Methods of Protecting Elevated Polysilicon Structures During Etching Processes 有权
标题翻译：在蚀刻过程中保护高架多晶硅结构的方法
公开(公告)号：US20130149851A1
公开(公告)日：2013-06-13
申请号：US13314270
申请日：2011-12-08
申请人： Liang Li , Huang Liu , Alex See , Soh Yun Siah , Xue Song Rao , Peng Zhou
发明人： Liang Li , Huang Liu , Alex See , Soh Yun Siah , Xue Song Rao , Peng Zhou
IPC分类号： H01L21/28
CPC分类号： H01L27/11534 , H01L21/28273
摘要： Disclosed herein are various methods of protecting elevated polysilicon structures during etching processes. In one example, the method includes forming a layer stack above a semiconducting substrate for a memory device, forming a protective mask layer above the layer stack of the memory device and performing at least one etching process to define a gate electrode for a transistor while the protective mask is in position above the layer stack for the memory device.
摘要翻译：本文公开了在蚀刻工艺期间保护升高的多晶硅结构的各种方法。在一个示例中，该方法包括在用于存储器件的半导体衬底之上形成层堆叠，在存储器件的层堆叠之上形成保护掩模层，并执行至少一个蚀刻工艺以限定晶体管的栅电极，而保护罩位于存储器件的层堆叠之上。

7. 发明授权

US06350661B2 Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contacts 失效
标题翻译：氮化硅封装的浅沟槽隔离方法，用于制造具有无边界接触的亚微米器件
公开(公告)号：US06350661B2
公开(公告)日：2002-02-26
申请号：US09882682
申请日：2001-06-18
申请人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
发明人： Chong Wee Lim , Eng Hua Lim , Soh Yun Siah , Kong Hean Lee , Chun Hui Low
IPC分类号： H01L2176
CPC分类号： H01L21/76232 , H01L21/76897
摘要： An improved and new process for fabricating MOSFET's in shallow trench isolation (STI), with sub-quarter micron ground rules, includes a passivating trench cap layer of silicon nitride. The silicon nitride passivating trench cap is utilized in the formation of borderless or “unframed” electrical contacts, without reducing the poly to poly spacing. Borderless contacts are formed, wherein contact openings are etched in an interlevel dielectric (ILD) layer over both an active region (P-N junction) and an inactive trench isolation region. During the contact hole opening, a selective etch process is utilized which etches the ILD layer, while the protecting passivating silicon nitride trench cap layer remains intact protecting the P-N junction at the edge of trench region. Subsequent processing of conductive tungsten metal plugs are prevented from shorting by the passivating trench cap. This method of forming borderless contacts with a passivating trench cap in a partially recessed trench isolation scheme improves device reliability since it prevents electrically short circuiting of the P-N junction and lowers the overall diode leakage. Furthermore, the use of the silicon nitride trench cap protects the underlying STI trench oxide during subsequent cleaning process steps. In addition, the nitride cap protects the STI oxide from excessive recess formation and prevents the exposure of STI seams, in addition to minimizing transistor junction leakage.
摘要翻译：具有亚四分之一微米基准规则的在浅沟槽隔离（STI）中制造MOSFET的改进和新工艺包括氮化硅的钝化沟槽盖层。氮化硅钝化沟槽帽用于形成无边界或“非成形”的电触头，而不会减少聚对多晶间距。形成无边界接触，其中接触开口在有源区（P-N结）和无源沟槽隔离区之上的层间电介质（ILD）层中被蚀刻。在接触孔打开期间，利用蚀刻ILD层的选择性蚀刻工艺，而保护性钝化氮化硅沟槽覆盖层保持完好，保护沟槽区域边缘处的P-N结。防止导电钨金属插塞的后续处理被钝化沟槽盖短路。这种在部分凹陷的沟槽隔离方案中与钝化沟槽盖形成无边界接触的方法提高了器件的可靠性，因为它防止了P-N结的电短路并降低了整体的二极管泄漏。此外，在随后的清洁工艺步骤中，使用氮化硅沟槽帽保护下面的STI沟槽氧化物。此外，除了最小化晶体管结漏电外，氮化物盖还可保护STI氧化物免于过度的凹陷形成，并防止STI接缝的暴露。

8. 发明授权

US08759947B2 Back-side MOM/MIM devices 有权
标题翻译：背面MOM / MIM设备
公开(公告)号：US08759947B2
公开(公告)日：2014-06-24
申请号：US13430778
申请日：2012-03-27
申请人： Juan Boon Tan , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah , Shunqiang Gong
发明人： Juan Boon Tan , Yeow Kheng Lim , Shao Ning Yuan , Soh Yun Siah , Shunqiang Gong
IPC分类号： H01L21/02
CPC分类号： H01L23/5223 , H01L23/481 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： Back-side MOM/MIM structures are integrated on a device with front-side circuitry. Embodiments include forming a substrate having a front side and a back side that is opposite the front side, the substrate including circuitry on the front side of the substrate; and forming a metal-oxide-metal (MOM) capacitor, a metal-insulator-metal (MIM) capacitor, or a combination thereof on the back side of the substrate. Other embodiments include forming a through-silicon via (TSV), in the substrate, connecting the MOM capacitor, the MIM capacitor, or a combination thereof to the circuitry on the front side of the substrate.
摘要翻译：背面MOM / MIM结构集成在具有前端电路的设备上。实施例包括形成具有与前侧相对的前侧和后侧的基板，所述基板在基板的正面上包括电路; 以及在衬底的背面上形成金属 - 氧化物 - 金属（MOM）电容器，金属 - 绝缘体 - 金属（MIM）电容器或其组合。其他实施例包括在衬底中形成穿硅通孔（TSV），将MOM电容器，MIM电容器或其组合连接到衬底前侧上的电路。

9. 发明授权

US08569173B2 Methods of protecting elevated polysilicon structures during etching processes 有权
标题翻译：在蚀刻过程中保护高架多晶硅结构的方法
公开(公告)号：US08569173B2
公开(公告)日：2013-10-29
申请号：US13314270
申请日：2011-12-08
申请人： Liang Li , Huang Liu , Alex See , Soh Yun Siah , Xue Song Rao , Peng Zhou
发明人： Liang Li , Huang Liu , Alex See , Soh Yun Siah , Xue Song Rao , Peng Zhou
IPC分类号： H01L21/302
CPC分类号： H01L27/11534 , H01L21/28273
摘要： Disclosed herein are various methods of protecting elevated polysilicon structures during etching processes. In one example, the method includes forming a layer stack above a semiconducting substrate for a memory device, forming a protective mask layer above the layer stack of the memory device and performing at least one etching process to define a gate electrode for a transistor while the protective mask is in position above the layer stack for the memory device.
摘要翻译：本文公开了在蚀刻工艺期间保护升高的多晶硅结构的各种方法。在一个示例中，该方法包括在用于存储器件的半导体衬底之上形成层堆叠，在存储器件的层堆叠之上形成保护掩模层，并执行至少一个蚀刻工艺以限定晶体管的栅电极，而保护罩位于存储器件的层堆叠之上。

10. 发明授权

US06762085B2 Method of forming a high performance and low cost CMOS device 有权
标题翻译：形成高性能和低成本CMOS器件的方法
公开(公告)号：US06762085B2
公开(公告)日：2004-07-13
申请号：US10262169
申请日：2002-10-01
申请人： Jia Zhen Zheng , Soh Yun Siah , Liang Choo Hsia , Eng Hua Lim , Simon Chooi , Chew Hoe Ang
发明人： Jia Zhen Zheng , Soh Yun Siah , Liang Choo Hsia , Eng Hua Lim , Simon Chooi , Chew Hoe Ang
IPC分类号： H01L218238
CPC分类号： H01L29/66598 , H01L21/823814 , H01L21/823835 , H01L21/823864
摘要： A method of fabricating a CMOS device with reduced processing costs as a result of a reduction in photolithographic masking procedures, has been developed. The method features formation of L shaped silicon oxide spacers on the sides of gate structures, with a vertical spacer component located on the sides of the gate structure, and with horizontal spacer components located on the surface of the semiconductor substrate with a thick horizontal spacer component located adjacent to the gate structures, while a thinner horizontal spacer component is located adjacent to the thicker horizontal spacer component. After formation of a block out shape in a PMOS region of the CMOS device, a high angle implantation procedure is used to form a P type halo region in a top portion of the NMOS region, followed by another implantation procedure performed at lower implant angles, resulting in an N type LDD region in a portion of the NMOS region underlying the thicker horizontal spacer component, and resulting in an N type heavily doped source/drain region in a portion of the NMOS underlying the thinner horizontal spacer component. Another block out shape, and another series of similar implantation procedures is performed to create the halo, LDD and source/drain regions in the PMOS region. After formation of a photoresist block out shape on specific CMOS regions, a composite insulator spacer is formed on the sides of gate structures not covered by the photoresist shape, followed by formation of metal silicide on the gate structures and source/drain regions not covered by the photoresist block out shape.
摘要翻译：已经开发了由于光刻掩模程序的减少而制造具有降低的处理成本的CMOS器件的方法。该方法特征是在栅极结构的侧面上形成L形氧化硅间隔物，其中垂直间隔件部件位于栅极结构的侧面，并且水平间隔件部件位于半导体衬底的表面上，具有厚的水平间隔件位于邻近门结构的位置，而较薄的水平间隔件组件位于较厚的水平间隔件部件附近。在CMOS器件的PMOS区域中形成块状形状之后，使用高角度注入工艺在NMOS区域的顶部形成P型卤素区域，随后以较低的注入角度进行另一种注入工艺，导致在较厚的水平间隔器部件下面的NMOS区域的一部分中的N型LDD区域，并且导致在较薄的水平间隔器部件下面的NMOS的一部分中的N型重掺杂的源极/漏极区域。执行另一个块状形状，并且进行另一系列相似的注入工艺以在PMOS区域中产生卤素，LDD和源极/漏极区域。在特定CMOS区域上形成光致抗蚀剂阻挡形状之后，在未被光致抗蚀剂形状覆盖的栅极结构的侧面上形成复合绝缘体间隔物，然后在栅极结构和未被覆盖的源极/漏极区域上形成金属硅化物光致抗蚀剂阻挡形状。

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