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1. 发明申请

US20090250818A1 VIA ELECTROMIGRATION IMPROVEMENT BY CHANGING THE VIA BOTTOM GEOMETRIC PROFILE 有权
标题翻译：通过改变通过底部几何轮廓的电力改进
公开(公告)号：US20090250818A1
公开(公告)日：2009-10-08
申请号：US12486521
申请日：2009-06-17
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L23/522
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

2. 发明授权

US07781895B2 Via electromigration improvement by changing the via bottom geometric profile 有权
公开(公告)号：US07781895B2
公开(公告)日：2010-08-24
申请号：US12486521
申请日：2009-06-17
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

3. 发明授权

US07691739B2 Via electromigration improvement by changing the via bottom geometric profile 有权
标题翻译：通过改变通孔底部几何轮廓来改善电迁移
公开(公告)号：US07691739B2
公开(公告)日：2010-04-06
申请号：US11374848
申请日：2006-03-13
申请人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Bei Chao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

4. 发明授权

US07045455B2 Via electromigration improvement by changing the via bottom geometric profile 有权
标题翻译：通过改变通孔底部几何轮廓来改善电迁移
公开(公告)号：US07045455B2
公开(公告)日：2006-05-16
申请号：US10692028
申请日：2003-10-23
申请人： Beichao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
发明人： Beichao Zhang , Chun Hui Low , Hong Lim Lee , Sang Yee Loong , Qiang Guo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

5. 发明授权

US06492242B1 Method of forming of high K metallic dielectric layer 失效
标题翻译：形成高K金属介电层的方法
公开(公告)号：US06492242B1
公开(公告)日：2002-12-10
申请号：US09609447
申请日：2000-07-03
申请人： Alex See , Cher Liang Randall Cha , Shyuz Fong Quek , Ting Cheong Ang , Wye Boon Loh , Sang Yee Loong , Jun Song , Chua Chee Tee
发明人： Alex See , Cher Liang Randall Cha , Shyuz Fong Quek , Ting Cheong Ang , Wye Boon Loh , Sang Yee Loong , Jun Song , Chua Chee Tee
IPC分类号： H01L2120
CPC分类号： H01L28/40 , H01L21/31683
摘要： A process for forming a high dielectric constant, (High K), layer, for a metal-oxide-metal, capacitor structure, featuring localized oxidation of an underlying metal layer, performed at a temperature higher than the temperature experienced by surrounding structures, has been developed. A first iteration of this process features the use of a laser ablation procedure, performed to a local region of an underlying metal layer, in an oxidizing ambient. The laser ablation procedure creates the desired, high temperature, only at the laser spot, allowing a high K layer to be created at this temperature, while the surrounding structures on a semiconductor substrate, not directly exposed to the laser ablation procedure remain at lower temperatures. A second iteration features the exposure of specific regions of an underlying metal layer, to a UV, or to an I line exposure procedure, performed in an oxidizing ambient, with the regions of an underlying metal layer exposed to the UV or I line procedure, via clear regions in an overlying photolithographic plate. This procedure also results in the formation of a high K layer, on a top portion of the underlying metal layer.
摘要翻译：在高于周围结构所经历的温度的温度下进行的金属氧化物 - 金属电容器结构的高介电常数（高K）层，其特征在于底层金属层的局部氧化，已经开发该方法的第一次迭代的特征在于在氧化环境中使用对底层金属层的局部区域进行的激光烧蚀程序。激光烧蚀过程仅在激光点产生所需的高温，允许在该温度下产生高K层，而不直接暴露于激光烧蚀过程的半导体衬底上的周围结构保持在较低温度。第二次迭代的特征在于在氧化环境中进行的底层金属层的特定区域到UV或I线曝光程序，暴露于UV或I线程序的下面的金属层的区域，通过覆盖光刻板中的透明区域。该过程还导致在下面的金属层的顶部上形成高K层。

6. 发明授权

US06258677B1 Method of fabricating wedge isolation transistors 失效
标题翻译：楔形隔离晶体管的制造方法
公开(公告)号：US06258677B1
公开(公告)日：2001-07-10
申请号：US09409875
申请日：1999-10-01
申请人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
发明人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
IPC分类号： H01L21336
CPC分类号： H01L29/0847 , H01L21/76264 , H01L21/76278 , H01L21/76283 , H01L21/823878 , H01L29/41783 , H01L29/66545 , H01L29/66628 , H01L29/66651
摘要： A method of fabricating a transistor, comprising the following steps. A silicon semiconductor structure having spaced, raised, wedge-shaped dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed. No HDP process trench fill is required to form the STIs and no CMP process is required to planarized the STIs.
摘要翻译：一种制造晶体管的方法，包括以下步骤。提供了具有限定其间的有源区域的具有间隔开的凸起的楔形介电隔离区域的硅半导体结构。在活性区域上生长外延硅以形成SEG区域。在SEG区域上形成一个虚拟门。凸起的外延硅层生长在与虚拟栅极相邻的SEG区域上。去除虚拟栅极，暴露凸起的外延硅层的内侧壁。在凸起的外延硅层的暴露的侧壁上形成侧壁间隔物。栅极氧化物层生长在SEG区域上并且在凸起的外延硅层的侧壁间隔物之间。在该结构上沉积一层多晶硅，并将其平坦化，以在SEG区域和凸出的外延硅层的侧壁间隔物之间形成栅极导体。去除侧壁间隔物。不需要HDP工艺沟槽填充来形成STI，并且不需要CMP工艺来平坦化STI。

7. 发明授权

US06248618B1 Method of fabrication of dual gate oxides for CMOS devices 有权
标题翻译：制造CMOS器件双栅氧化物的方法
公开(公告)号：US06248618B1
公开(公告)日：2001-06-19
申请号：US09415246
申请日：1999-10-12
申请人： Shyue Fong Quek , Ting Cheong Ang , Puay Ing Ong , Sang Yee Loong
发明人： Shyue Fong Quek , Ting Cheong Ang , Puay Ing Ong , Sang Yee Loong
IPC分类号： H01L218238
CPC分类号： H01L21/823857 , Y10S438/981
摘要： A method of forming thick and thin gate oxides comprising the following steps. A silicon semiconductor substrate having first and second active areas separated by shallow isolation trench regions is provided. Oxide growth is selectively formed over the first active area by UV oxidation to form a first gate oxide layer having a first predetermined thickness. The first and second active areas are then simultaneously oxidized whereby the first predetermined thickness of the first gate oxide layer is increased to a second predetermined thickness and a second gate oxide layer having a predetermined thickness is formed in the second active area. The second predetermined thickness of the first oxide layer in the first active area is greater than the predetermined thickness of the second oxide layer in the second active area.
摘要翻译：一种形成厚薄的栅极氧化物的方法，包括以下步骤。提供具有由浅隔离沟槽区域隔开的第一和第二有源区的硅半导体衬底。通过UV氧化在第一有源区上选择性地形成氧化物生长，以形成具有第一预定厚度的第一栅氧化层。然后，第一和第二有源区域被同时氧化，由此第一栅极氧化物层的第一预定厚度增加到第二预定厚度，并且在第二有源区域中形成具有预定厚度的第二栅极氧化物层。第一有源区中的第一氧化物层的第二预定厚度大于第二有源区中第二氧化物层的预定厚度。

8. 发明授权

US06611024B2 Method of forming PID protection diode for SOI wafer 有权
公开(公告)号：US06611024B2
公开(公告)日：2003-08-26
申请号：US09946981
申请日：2001-09-06
申请人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
发明人： Ting Cheong Ang , Shyue Fong Quek , Sang Yee Loong , Jun Song
IPC分类号： H01L2701
CPC分类号： H01L21/84 , H01L27/1203
摘要： An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

9. 发明授权

US06465296B1 Vertical source/drain contact semiconductor 有权
标题翻译：垂直源极/漏极接触半导体
公开(公告)号：US06465296B1
公开(公告)日：2002-10-15
申请号：US10167095
申请日：2002-06-10
申请人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
发明人： Shyue Fong Quek , Ting Cheong Ang , Sang Yee Loong , Puay Ing Ong
IPC分类号： H01L218238
CPC分类号： H01L29/66772 , H01L21/76264 , H01L21/76281 , H01L29/41733 , H01L29/458 , H01L29/66636 , H01L29/66825 , H01L29/78621
摘要： A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.
摘要翻译：提供了一种半导体器件及其制造方法，其中倾斜的掺杂剂注入之后是在与半导体栅极的侧面相邻的绝缘体上硅衬底中形成垂直沟槽。暴露在源极/漏极结中的第二掺杂剂注入之后是在衬底中形成半导体沟道的快速热退火。然后形成在半导体衬底中具有向内弯曲的横截面宽度的触头，其直接地或通过咸水接触区域垂直连接到暴露的源极/漏极接合点。

10. 发明授权

US06406994B1 Triple-layered low dielectric constant dielectric dual damascene approach 有权
标题翻译：三层低介电常数电介质双镶嵌方法
公开(公告)号：US06406994B1
公开(公告)日：2002-06-18
申请号：US09726657
申请日：2000-11-30
申请人： Ting Cheong Ang , Shyue Fong Quek , Yee Chong Wong , Sang Yee Loong
发明人： Ting Cheong Ang , Shyue Fong Quek , Yee Chong Wong , Sang Yee Loong
IPC分类号： H01L2144
CPC分类号： B41M5/5254 , B41M5/508 , B41M5/5218 , B41M5/5272 , Y10T428/24802
摘要： A triple layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material. If the first type is a low dielectric constant inorganic material, the second type will be a low dielectric constant organic material.
摘要翻译：描述了三层低介电常数材料双镶嵌金属化工艺。金属线被覆盖在半导体衬底上的绝缘层所覆盖。第一类型的第一介电层沉积在绝缘层上。第二类型的第二介电层沉积在第一介电层上。通孔图案被蚀刻到第二介电层中。此后，第一类型的第三电介质层沉积在图案化的第二介电层上。同时，沟槽图案被蚀刻到第三介电层中，并且通孔图案被蚀刻到第一介电层中，以在集成电路器件的制造中完成双镶嵌开口的形成。如果第一种类型是低介电常数有机材料，则第二种类型将是低介电常数无机材料。如果第一种类型是低介电常数无机材料，则第二类型将是低介电常数有机材料。

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