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1. 发明授权

US07102446B1 Phase lock loop with coarse control loop having frequency lock detector and device including same 有权
标题翻译：具有粗调控制回路的锁相环具有频率锁定检测器和包括其的装置
公开(公告)号：US07102446B1
公开(公告)日：2006-09-05
申请号：US11056995
申请日：2005-02-11
申请人： Hyung-Rok Lee , Moon-Sang Hwang , Sang-Hyun Lee , Bong-Joon Lee , Deog-Kyoon Jeong
发明人： Hyung-Rok Lee , Moon-Sang Hwang , Sang-Hyun Lee , Bong-Joon Lee , Deog-Kyoon Jeong
IPC分类号： H03L7/07 , H03L7/087 , H04B1/40 , H04B1/50
CPC分类号： H03L7/087 , H03K23/507 , H03L7/089 , H03L7/093 , H03L7/099 , H03L7/0995 , H03L7/10 , H03L2207/06 , H04L7/0337 , Y10S331/02
摘要： A phase lock loop (PLL) for controlling a sampling clock or other clock, and a data sampling circuit, transceiver, or other device including such a PLL. The PLL includes a multi-range VCO, at least one fine control loop for controlling the VCO, and a coarse control loop for controlling the VCO by changing its frequency-voltage characteristic. The coarse control loop includes a frequency lock detector and voltage range monitoring logic. Typically, the frequency lock detector locks operation of the coarse control loop when the difference between the VCO output clock frequency and a reference frequency decreases to within a predetermined threshold, and the unlocked coarse control loop employs the voltage range monitoring logic to change the VCO frequency-voltage characteristic when the VCO's fine control voltage leaves a predetermined range. Other aspects are a transceiver (including at least two receiver interfaces and a transmitter interface) implementing a clocking scheme employing no more than three PLLs for clock generation, and a transceiver having a multi-layered receiver interface including digital circuitry and a single clock-generating PLL (an analog PLL for generating a multiphase clock to be shared by all layers of the receiver interface). Each receiver interface layer performs blind oversampling on a different received signal using the multiphase clock and the digital circuitry includes multilayered digital phase lock loop circuitry which receives the oversampled data.
摘要翻译：用于控制采样时钟或其他时钟的锁相环（PLL）以及数据采样电路，收发器或包括这种PLL的其它装置。 PLL包括多范围VCO，用于控制VCO的至少一个精细控制环路和用于通过改变其频率 - 电压特性来控制VCO的粗略控制环路。粗调控制回路包括一个频率锁定检测器和电压范围监控逻辑。通常，当VCO输出时钟频率和参考频率之间的差减小到预定阈值时，频率锁定检测器锁定粗略控制环路的操作，而解锁的粗略控制环路采用电压范围监控逻辑来改变VCO频率当VCO的精细控制电压离开预定范围时的电压特性。其他方面是实现采用不超过三个PLL用于时钟产生的时钟方案的收发器（包括至少两个接收器接口和发射器接口），以及具有包括数字电路和单个时钟产生的多层接收器接口的收发器 PLL（用于产生要由接收器接口的所有层共享的多相时钟的模拟PLL）。每个接收器接口层使用多相时钟在不同的接收信号上执行盲过采样，并且数字电路包括接收过采样数据的多层数字锁相环电路。

2. 发明授权

US07409031B1 Data sampling method and apparatus with alternating edge sampling phase detection for loop characteristic stabilization 有权
标题翻译：具有交替边缘采样相位检测的数据采样方法和装置，用于环路特性稳定
公开(公告)号：US07409031B1
公开(公告)日：2008-08-05
申请号：US10642259
申请日：2003-08-15
申请人： Bong-Joon Lee , Moon-Sang Hwang , Sang-Hyun Lee , Deog-Kyoon Jeong
发明人： Bong-Joon Lee , Moon-Sang Hwang , Sang-Hyun Lee , Deog-Kyoon Jeong
IPC分类号： H03D3/24
CPC分类号： H03L7/10 , H03L7/07 , H03L7/0805 , H03L7/0891 , H03L7/0995 , H03L7/107 , H04L7/0083 , H04L7/0091 , H04L7/033
摘要： A method and apparatus for 2× oversampling of data having jitter. In some embodiments, the invention is a clock and data recovery device including an alternating edge sampling binary phase detector, and which is configured to stabilize loop characteristics in various jitter environments and can be implemented with small hardware overhead. A transceiver that embodies the invention can be implemented as a CMOS integrated circuit using a 0.18 μm CMOS process, with the transceiver chip being capable of recovering data having a data rate of up to 11.5 Gbps from a signal received over a serial link, while consuming no more than 540 mW from 1.8V supply, and with a bit error rate of less than 10−12.
摘要翻译：一种用于对具有抖动的数据进行2x过采样的方法和装置。在一些实施例中，本发明是包括交替边缘采样二进制相位检测器的时钟和数据恢复装置，其被配置为稳定各种抖动环境中的环路特性，并且可以以小的硬件开销来实现。实现本发明的收发器可以被实现为使用0.18mum CMOS工艺的CMOS集成电路，收发器芯片能够从消耗串行链路接收的信号中恢复具有高达11.5Gbps的数据速率的数据，同时消耗 1.8V电源不超过540mW，误码率小于10 -12 。

3. 发明申请

US20120206176A1 COARSE LOCK DETECTOR AND DELAY-LOCKED LOOP INCLUDING THE SAME 有权
标题翻译：包括锁定锁定检测器和延迟锁定环路
公开(公告)号：US20120206176A1
公开(公告)日：2012-08-16
申请号：US13398245
申请日：2012-02-16
申请人： Moon-Sang Hwang , Won-Jun Choe , Han-Kyu Chi , Deog-Kyoon Jeong
发明人： Moon-Sang Hwang , Won-Jun Choe , Han-Kyu Chi , Deog-Kyoon Jeong
IPC分类号： H03L7/08
CPC分类号： H03L7/0812 , H03L7/095 , H03L7/101
摘要： A coarse lock detector is disclosed. The course lock detector uses an initial lock range to determine course lock, and once course lock is achieved, uses a modified lock range to determine course lock.
摘要翻译：公开了一种粗锁检测器。课程锁定检测器使用初始锁定范围来确定课程锁定，并且一旦达到课程锁定，则使用修改的锁定范围来确定课程锁定。

4. 发明申请

US20120206185A1 LEVEL-DOWN SHIFTER 有权
标题翻译：水平下降
公开(公告)号：US20120206185A1
公开(公告)日：2012-08-16
申请号：US13357654
申请日：2012-01-25
申请人： Moon-Sang Hwang , Won-Jun Choe , Hyun-Chang Kim , Deog-Kyoon Jeong
发明人： Moon-Sang Hwang , Won-Jun Choe , Hyun-Chang Kim , Deog-Kyoon Jeong
IPC分类号： H03L5/00
CPC分类号： H03K19/018528
摘要： A level-down shifter includes: a first load device between a first voltage and a first node; a second load device between the first voltage and a second node; a first input device between the first node and a third node, receiving a reference voltage signal, and adjusting a first node voltage of the first node based on the reference voltage signal; a second input device between the second node and the third node, receiving an input signal, and adjusting a second node voltage of the second node based on the input signal; and a current source between a second voltage and the third node, receiving the second node voltage of the second node, and adjusting a third node voltage of the third node and a bias current based on the second node voltage of the second node, wherein a level of the input signal is higher than the first voltage.
摘要翻译：电平降低移位器包括：第一电压和第一节点之间的第一负载装置; 在所述第一电压和第二节点之间的第二负载装置; 在所述第一节点和第三节点之间的第一输入装置，接收参考电压信号，以及基于所述参考电压信号调整所述第一节点的第一节点电压; 在所述第二节点和所述第三节点之间的第二输入设备，接收输入信号，以及基于所述输入信号调整所述第二节点的第二节点电压; 以及第二电压和第三节点之间的电流源，接收第二节点的第二节点电压，以及基于第二节点的第二节点电压调整第三节点的第三节点电压和偏置电流，其中，输入信号的电平高于第一电压。

5. 发明授权

US08729937B2 Coarse lock detector 有权
标题翻译：粗锁检测器
公开(公告)号：US08729937B2
公开(公告)日：2014-05-20
申请号：US13398532
申请日：2012-02-16
申请人： Moon-Sang Hwang , Won-Jun Choe , Han-Kyu Chi , Deog-Kyoon Jeong
发明人： Moon-Sang Hwang , Won-Jun Choe , Han-Kyu Chi , Deog-Kyoon Jeong
IPC分类号： H03L7/00
CPC分类号： H03L7/095 , H03L7/0812 , H03L7/101
摘要： A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.
摘要翻译：公开了一种用于延迟锁定环（DLL）的粗略锁定检测器。粗锁检测器包括多个检测单元。每个检测单元接收延迟时钟相位和先前检测单元的输出作为输入。为了增加先前检测单元的输出的时间传播，检测单元被分组排列，使得来自先前检测单元的输出是由多于一个先前检测单元的检测单元生成的。

6. 发明授权

US08829969B2 Level-down shifter 有权
标题翻译：降档移位器
公开(公告)号：US08829969B2
公开(公告)日：2014-09-09
申请号：US13357654
申请日：2012-01-25
申请人： Moon-Sang Hwang , Won-Jun Choe , Hyun-Chang Kim , Deog-Kyoon Jeong
发明人： Moon-Sang Hwang , Won-Jun Choe , Hyun-Chang Kim , Deog-Kyoon Jeong
IPC分类号： H03L5/00
CPC分类号： H03K19/018528
摘要： A level-down shifter includes: a first load device between a first voltage and a first node; a second load device between the first voltage and a second node; a first input device between the first node and a third node, receiving a reference voltage signal, and adjusting a first node voltage of the first node based on the reference voltage signal; a second input device between the second node and the third node, receiving an input signal, and adjusting a second node voltage of the second node based on the input signal; and a current source between a second voltage and the third node, receiving the second node voltage of the second node, and adjusting a third node voltage of the third node and a bias current based on the second node voltage of the second node, wherein a level of the input signal is higher than the first voltage.
摘要翻译：电平降低移位器包括：第一电压和第一节点之间的第一负载装置; 在所述第一电压和第二节点之间的第二负载装置; 在所述第一节点和第三节点之间的第一输入装置，接收参考电压信号，以及基于所述参考电压信号调整所述第一节点的第一节点电压; 在所述第二节点和所述第三节点之间的第二输入设备，接收输入信号，以及基于所述输入信号调整所述第二节点的第二节点电压; 以及第二电压和第三节点之间的电流源，接收第二节点的第二节点电压，以及基于第二节点的第二节点电压调整第三节点的第三节点电压和偏置电流，其中，输入信号的电平高于第一电压。

7. 发明授权

US08587355B2 Coarse lock detector and delay-locked loop including the same 有权
标题翻译：粗锁检测器和延迟锁定回路包括相同的
公开(公告)号：US08587355B2
公开(公告)日：2013-11-19
申请号：US13398245
申请日：2012-02-16
申请人： Moon-Sang Hwang , Won-Jun Choe , Han-Kyu Chi , Deog-Kyoon Jeong
发明人： Moon-Sang Hwang , Won-Jun Choe , Han-Kyu Chi , Deog-Kyoon Jeong
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/095 , H03L7/101
摘要： A coarse lock detector is disclosed. The course lock detector uses an initial lock range to determine course lock, and once course lock is achieved, uses a modified lock range to determine course lock.
摘要翻译：公开了一种粗锁检测器。课程锁定检测器使用初始锁定范围来确定课程锁定，并且一旦达到课程锁定，则使用修改的锁定范围来确定课程锁定。

8. 发明申请

US20120212264A1 COARSE LOCK DETECTOR 有权
标题翻译：听力锁定检测器
公开(公告)号：US20120212264A1
公开(公告)日：2012-08-23
申请号：US13398532
申请日：2012-02-16
申请人： Moon-Sang Hwang , Won-Jun Choe , Han-Kyu Chi , Deog-Kyoon Jeong
发明人： Moon-Sang Hwang , Won-Jun Choe , Han-Kyu Chi , Deog-Kyoon Jeong
IPC分类号： H03L7/00
CPC分类号： H03L7/095 , H03L7/0812 , H03L7/101
摘要： A coarse lock detector for a delayed locked loop (DLL) is disclosed. The coarse lock detector includes multiple detection cells. Each detection cell receives a delayed clock phase and an output of a previous detection cell as inputs. To increase time for the output of the previous detection cell to propagate, the detection cells are arranged in groups such that the output from the previous detection cell is generated by a detection cell which is more than one detection cell previous.
摘要翻译：公开了一种用于延迟锁定环（DLL）的粗略锁定检测器。粗锁检测器包括多个检测单元。每个检测单元接收延迟时钟相位和先前检测单元的输出作为输入。为了增加先前检测单元的输出的时间传播，检测单元被分组排列，使得来自先前检测单元的输出是由多于一个先前检测单元的检测单元生成的。

9. 发明授权

US06819166B1 Continuous-time, low-frequency-gain/high-frequency-boosting joint adaptation equalizer and method 有权
标题翻译：连续时间，低频增益/高频增强联合适应均衡器和方法
公开(公告)号：US06819166B1
公开(公告)日：2004-11-16
申请号：US10403477
申请日：2003-03-31
申请人： Jong-Sang Choi , Moon-Sang Hwang , Deog-Kyoon Jeong
发明人： Jong-Sang Choi , Moon-Sang Hwang , Deog-Kyoon Jeong
IPC分类号： H03O100
CPC分类号： H04L25/03025 , H04L25/03885
摘要： In a class of embodiments, an adaptive equalization circuit that implements a joint adaptation algorithm. Other embodiments are receivers that include such an adaptive equalization circuit, and joint adaptation equalization methods. The equalization circuit includes a filter having a low-frequency-gain path (sometimes referred to as a low-frequency filter) and a high-frequency-boosting path (sometimes referred to as a high-frequency filter). The high-frequency filter typically includes a high-pass filter in series with an amplifier having adjustable gain. A high-frequency-boosting tuning loop controls the adjustable gain applied by the high-frequency filter. A low-frequency-gain tuning loop controls the adjustable gain applied by the low-frequency filter.
摘要翻译：在一类实施例中，实现联合自适应算法的自适应均衡电路。其他实施例是包括这种自适应均衡电路和联合适应均衡方法的接收机。均衡电路包括具有低频增益路径（有时称为低频滤波器）和高频增强路径（有时称为高频滤波器）的滤波器。高频滤波器通常包括与具有可调增益的放大器串联的高通滤波器。高频提升调谐环控制由高频滤波器施加的可调增益。低频增益调谐回路控制低频滤波器施加的可调增益。

10. 发明申请

US20070098112A1 Clock-edge modulated serial link with DC-balance control 有权
标题翻译：具有直流平衡控制的时钟调制串行链路
公开(公告)号：US20070098112A1
公开(公告)日：2007-05-03
申请号：US11264303
申请日：2005-10-31
申请人： Gyudong Kim , Won Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
发明人： Gyudong Kim , Won Choe , Deog-Kyoon Jeong , Jaeha Kim , Bong-Joon Lee , Min-Kyu Kim
IPC分类号： H04L27/04 , H04B3/00
CPC分类号： H04L7/0008 , H04L25/0272 , H04L25/0284 , H04L25/4902
摘要： A battery powered computing device has a channel configured as a single direct current balanced differential channel. A signal transmitter is connected to the channel. The signal transmitter is configured to apply clock edge modulated signals to the channel, where the clock edge modulated signals include direct current balancing control signals. A signal receiver is connected to the channel. The signal receiver is configured to recover the direct current balancing control signals.
摘要翻译：电池供电的计算设备具有被配置为单个直流平衡差分通道的通道。信号发射器连接到通道。信号发射器被配置为将时钟边缘调制信号施加到信道，其中时钟边缘调制信号包括直流平衡控制信号。信号接收器连接到通道。信号接收器被配置为恢复直流平衡控制信号。

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