专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07158593B2 Combining a clock signal and a data signal 有权
标题翻译：组合时钟信号和数据信号
公开(公告)号：US07158593B2
公开(公告)日：2007-01-02
申请号：US10099533
申请日：2002-03-15
申请人： Gyudong Kim , Ook Kim , Min-Kyu Kim , Bruce Kim , Seung Ho Hwang
发明人： Gyudong Kim , Ook Kim , Min-Kyu Kim , Bruce Kim , Seung Ho Hwang
IPC分类号： H04L7/00
CPC分类号： H04L25/4902 , G09G5/006 , H04L5/06 , H04L7/0008 , H04L7/0054 , H04L7/027
摘要： A method of transmitting data in a system including at least one data channel and a separate clock channel is disclosed. The method involves combining a clock signal to be transmitted on the clock channel with a data signal to generate a combined clock and data signal. In one embodiment, the data signal has been generated from data words using an encoding scheme that shifts an energy spectrum of the data signal away from an energy spectrum of the clock signal. In another embodiment, the clock signal has a plurality of pulses each having a front edge and a back edge, and the data signal is modulated onto the clock signal by moving at least one edge (i.e. front or back or both) of the plurality of pulses, thereby to create a combined clock and data signal.
摘要翻译：公开了一种在包括至少一个数据信道和单独的时钟信道的系统中发送数据的方法。该方法包括将要在时钟信道上发送的时钟信号与数据信号组合以产生组合的时钟和数据信号。在一个实施例中，数据信号已经使用使数据信号的能谱偏离时钟信号的能谱的编码方案从数据字生成。在另一个实施例中，时钟信号具有多个脉冲，每个脉冲具有前沿和后沿，并且数据信号通过移动多个脉冲的至少一个边缘（即，前面或背面或两者）被调制到时钟信号上脉冲，从而创建一个组合的时钟和数据信号。

2. 发明申请

US20090323830A1 CURRENT MODE CIRCUITRY TO MODULATE A COMMON MODE VOLTAGE 有权
标题翻译：电流模式电路来调制共模电压
公开(公告)号：US20090323830A1
公开(公告)日：2009-12-31
申请号：US12555300
申请日：2009-09-08
申请人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
发明人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
IPC分类号： H04B3/00 , H03K19/094 , H03K19/0175
CPC分类号： H04L5/20
摘要： In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片包括用于检测共模电压变化的共模检测电路。描述和要求保护其他实施例。

3. 发明授权

US07872498B2 Current mode circuitry to modulate a common mode voltage 有权
标题翻译：用于调制共模电压的电流模式电路
公开(公告)号：US07872498B2
公开(公告)日：2011-01-18
申请号：US12555300
申请日：2009-09-08
申请人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
发明人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
IPC分类号： H03K19/0175
CPC分类号： H04L5/20
摘要： In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片包括用于检测共模电压变化的共模检测电路。描述和要求保护其他实施例。

4. 发明授权

US07589559B2 Current mode circuitry to modulate a common mode voltage 有权
标题翻译：用于调制共模电压的电流模式电路
公开(公告)号：US07589559B2
公开(公告)日：2009-09-15
申请号：US11643388
申请日：2006-12-20
申请人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
发明人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
IPC分类号： H03K19/0175
CPC分类号： H04L5/20
摘要： In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片包括用于检测共模电压变化的共模检测电路。描述和要求保护其他实施例。

5. 发明申请

US20080169838A1 Current mode circuitry to modulate a common mode voltage 有权
标题翻译：用于调制共模电压的电流模式电路
公开(公告)号：US20080169838A1
公开(公告)日：2008-07-17
申请号：US11643388
申请日：2006-12-20
申请人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
发明人： Daeyun Shim , Min-Kyu Kim , Gyudong Kim , Keewook Jung , Seung Ho Hwang
IPC分类号： H01P5/00
CPC分类号： H04L5/20
摘要： In some embodiments, a chip includes transmitters to transmit differential signals on conductors; and current mode circuitry to selectively modulate a common mode voltage of the differential signals to communicate data. In other embodiments, a system includes a first chip to transmit first and second differential signals on conductors, and a second chip. The second chip includes receivers to receive the first and second differential signals from the conductors and provide received signals representative thereof, and current mode circuitry to selectively modulate a common mode voltage of either the first or second differential signals to communicate data and wherein the first chip includes common mode detection circuitry to detect changes in the common mode voltage. Other embodiments are described and claimed.
摘要翻译：在一些实施例中，芯片包括在导体上传输差分信号的发射器; 以及电流模式电路，用于选择性地调制差分信号的共模电压以传送数据。在其他实施例中，系统包括用于在导体上传输第一和第二差分信号的第一芯片和第二芯片。第二芯片包括接收器，用于从导体接收第一和第二差分信号并提供表示其的接收信号;以及电流模式电路，用于选择性地调制第一或第二差分信号的共模电压以传送数据，并且其中第一芯片包括用于检测共模电压变化的共模检测电路。描述和要求保护其他实施例。

6. 发明授权

US06463092B1 System and method for sending and receiving data signals over a clock signal line 有权
标题翻译：用于通过时钟信号线发送和接收数据信号的系统和方法
公开(公告)号：US06463092B1
公开(公告)日：2002-10-08
申请号：US09393235
申请日：1999-09-09
申请人： Gyudong Kim , Min-Kyu Kim , Seung Ho Hwang
发明人： Gyudong Kim , Min-Kyu Kim , Seung Ho Hwang
IPC分类号： H04B138
CPC分类号： G09G5/006 , G09G5/008 , G09G2370/04 , H04L7/0008 , H04L25/4902
摘要： The system preferably includes a unique transmitter that sends both clock and data signals over the same transmission line. The receiver uses the same transmission line to send data signals back to the transmitter. The transmitter comprises a clock generator, a decoder and a line interface. The clock generator produces a clock signal that includes a variable position falling edge. The falling edge position is decoded by the receiver to extract data from the clock signal. The receiver comprises a clock re-generator, a data decoder and a return channel encoder. The clock re-generator monitors the transmission line, receives signals, filters them and generates a clock signal at the receiver from the signal on the transmission line. The return channel encoder generates signals and asserts them on the transmission line. The signal is asserted or superimposed over the clock & data signal provided by the transmitter.
摘要翻译：该系统优选地包括在同一传输线上发送时钟和数据信号的唯一发射机。接收机使用相同的传输线将数据信号发送回发射机。发射机包括时钟发生器，解码器和线路接口。时钟发生器产生包括可变位置下降沿的时钟信号。下降沿位置被接收器解码以从时钟信号中提取数据。接收机包括时钟再生器，数据解码器和返回通道编码器。时钟再发生器监视传输线，接收信号，对它们进行滤波，并在接收机上根据传输线上的信号产生时钟信号。返回通道编码器产生信号并在传输线上断言它们。该信号被断言或叠加在发射机提供的时钟和数据信号上。

7. 发明授权

US07269673B2 Cable with circuitry for asserting stored cable data or other information to an external device or user 有权
标题翻译：电缆，用于将存储的电缆数据或其他信息断言给外部设备或用户
公开(公告)号：US07269673B2
公开(公告)日：2007-09-11
申请号：US10781405
申请日：2004-02-18
申请人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Hoon Kim , Gijung Ahn , Seung Ho Hwang
发明人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Hoon Kim , Gijung Ahn , Seung Ho Hwang
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.
摘要翻译：包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。电缆可以包括导体，存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路，并且将所访问的数据串行地认定到至少一个导体（例如，用于传输到外部设备）。本发明的其他方面是用于访问存储在电缆中并且可选地使用数据（例如，实现均衡）的电缆数据的方法。电缆数据可以表示电缆类型，等级，速度，长度和阻抗的全部或一些，日期代码，频率相关衰减表，远端串扰和EMI相关系数，共模辐射，内部对歪斜等信息。电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色，亮度和/或闪烁图案的驱动信号的电路。

8. 发明授权

US07500032B2 Cable with circuitry for asserting stored cable data or other information to an external device or user 有权
标题翻译：电缆，用于断开存储的电缆数据或其他信息到外部设备或用户的电路
公开(公告)号：US07500032B2
公开(公告)日：2009-03-03
申请号：US11848758
申请日：2007-08-31
申请人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Hoon Kim , Gijung Ahn , Seung Ho Hwang
发明人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Hoon Kim , Gijung Ahn , Seung Ho Hwang
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.
摘要翻译：包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。电缆可以包括导体，存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路，并且将所访问的数据串行地认定到至少一个导体（例如，用于传输到外部设备）。本发明的其他方面是用于访问存储在电缆中并且可选地使用数据（例如，实现均衡）的电缆数据的方法。电缆数据可以表示电缆类型，等级，速度，长度和阻抗的全部或一些，日期代码，频率相关衰减表，远端串扰和EMI相关系数，共模辐射，内部对歪斜等信息。电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色，亮度和/或闪烁图案的驱动信号的电路。

9. 发明授权

US06870930B1 Methods and systems for TMDS encryption 有权
标题翻译： TMDS加密的方法和系统
公开(公告)号：US06870930B1
公开(公告)日：2005-03-22
申请号：US09579811
申请日：2000-05-26
申请人： Gyudong Kim , Victor M. Da Costa , Bruce Kim , David D. Lee , Russel A. Martin , Seung Ho Hwang
发明人： Gyudong Kim , Victor M. Da Costa , Bruce Kim , David D. Lee , Russel A. Martin , Seung Ho Hwang
IPC分类号： H04L9/08 , H04L9/12 , H04L9/18 , H04N7/167 , H04N7/173 , H04L9/00 , H04K1/06
CPC分类号： G09G5/006 , H04L9/065 , H04L9/0844 , H04L9/12 , H04L2209/046 , H04L2209/34 , H04L2209/605 , H04N7/1675 , H04N7/17318 , H04N21/23476 , H04N21/44055 , H04N21/63345
摘要： The present invention is directed to systems and methods for protecting digital content during transmission. One version of the invention provides a method for encryption in a high-speed digital video transmission system that includes the steps of: a) performing transition controlled encoding of a first sequence of n bit data words into encoded n+1 bit data characters where the n is a positive integer, b) performing XOR masking of the encoded n+1 bit data characters with an XOR mask to produce masked n+1 bit data characters; c) DC balancing the masked n+1 bit data characters to produce DC balanced, masked n+2 bit data characters; d) scrambling the DC balanced, masked n+2 bit data characters using a scrambling formula to produce encrypted n+2 bit data characters; e) encoding control data into encoded n+2 bit control characters, f) generating a serial data stream in response to the encrypted data characters and encoded control characters, and g) transmitting the serial data stream over a communication link. Subsequent to step (e) and prior to step (f), the method can further include the step of encrypting the encoded n+2 bit control characters, such that the generating step generates a serial data stream in response to the encrypted data characters and the encrypted control characters.
摘要翻译：本发明涉及用于在传输期间保护数字内容的系统和方法。本发明的一个方案提供了一种用于在高速数字视频传输系统中进行加密的方法，该方法包括以下步骤：a）对n位数据字的第一序列进行转换控制编码，以编码到编码的n + 1位数据字符中，其中 n是正整数，b）用XOR掩码执行编码的n + 1位数据字符的异或掩蔽，以产生掩蔽的n + 1位数据字符; c）直流平衡屏蔽的n + 1位数据字符，以产生直流平衡，屏蔽的n + 2位数据字符; d）使用扰频公式对DC平衡掩蔽的n + 2位数据字符进行加扰，以产生加密的n + 2位数据字符; e）将控制数据编码为编码的n + 2位控制字符，f）响应于加密的数据字符和编码的控制字符产生串行数据流，以及g）通过通信链路发送串行数据流。在步骤（e）之后和步骤（f）之后，该方法还可以包括对编码的n + 2位控制字符进行加密的步骤，使得生成步骤响应于加密的数据字符生成串行数据流，并且加密的控制字符。

10. 发明授权

US07236553B1 Reduced dead-cycle, adaptive phase tracking method and apparatus 有权
标题翻译：减少死循环，自适应相位跟踪方法和装置
公开(公告)号：US07236553B1
公开(公告)日：2007-06-26
申请号：US10763905
申请日：2004-01-23
申请人： Hoon Choi , Gyudong Kim , Daeyun Shim , Bruce Kim , Seung Ho Hwang
发明人： Hoon Choi , Gyudong Kim , Daeyun Shim , Bruce Kim , Seung Ho Hwang
IPC分类号： H04L7/00
CPC分类号： H04L7/0337 , H04L7/0008
摘要： A data sampling method and circuit employing an oversampling clock to oversample a data signal, a phase tracker for use with or in a data sampling circuit, and a method for identifying a sequence of best sampling positions for sampling a data signal from signal samples generated using an oversampling clock. In some embodiments, data indicative of the phase of at least one of the oversampling clock's sampling positions relative to the center of the data eye are low-pass filtered in a manner determined by the data signal's bit rate. In other embodiments, the number of dead cycles of the phase tracker decision loop is reduced by generating possible solutions in parallel and moving the feedback point so as to occur as late as practical, or the phase tracker ignores a sample set when updating its determination of the best sampling position when the sample set indicates that the data signal has less than a predetermined number of transitions during a corresponding tracking period.
摘要翻译：使用过采样时钟对数据信号进行过采样的数据采样方法和电路，与数据采样电路一起使用或在数据采样电路中使用的相位跟踪器，以及用于识别最佳采样位置序列的方法，用于从使用过采样时钟。在一些实施例中，指示相对于数据眼睛的中心的过采样时钟的采样位置中的至少一个的相位的数据以由数据信号的比特率确定的方式进行低通滤波。在其他实施例中，相位跟踪器判定循环的死循环的数量通过并行产生可能的解并且将反馈点移动以便尽可能晚地发生而减少，或者当更新其样本集的确定时，相位跟踪器忽略样本集当样本集合表示在对应的跟踪周期期间数据信号具有小于预定数量的转换时的最佳采样位置。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式