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1. 发明授权

US06888417B2 Voltage controlled oscillator 有权
标题翻译：压控振荡器
公开(公告)号：US06888417B2
公开(公告)日：2005-05-03
申请号：US10613442
申请日：2003-07-03
申请人： Yongsam Moon , Gijung Ahn , Deog-Kyoon Jeong
发明人： Yongsam Moon , Gijung Ahn , Deog-Kyoon Jeong
IPC分类号： H03L7/091 , H03L7/113 , H03L7/14 , H04L7/033 , H04L7/04 , H03B5/00 , H03F3/45
CPC分类号： H04L7/033 , H03L7/091 , H03L7/113 , H03L7/14 , H04L7/04 , Y10S331/02
摘要： A folded starved inverter differential output apparatus for use in a voltage controlled oscillator includes a first polarity of two transistors that are cross-coupled and a second polarity of four transistors. Also included are two inverter gates and a supply regulator.
摘要翻译：用于压控振荡器的折叠的饥饿型逆变器差分输出装置包括交叉耦合的两个晶体管的第一极性和四个晶体管的第二极性。还包括两个逆变器门和电源调节器。

2. 发明授权

US06560290B2 CMOS driver and on-chip termination for gigabaud speed data communication 有权
标题翻译： CMOS驱动器和片上终端，用于千兆位速度数据通信
公开(公告)号：US06560290B2
公开(公告)日：2003-05-06
申请号：US09234619
申请日：1999-01-20
申请人： Gijung Ahn , Deog-Kyoon Jeong , Gyudong Kim
发明人： Gijung Ahn , Deog-Kyoon Jeong , Gyudong Kim
IPC分类号： H04L2700
CPC分类号： H04L25/028 , H04L25/0272 , H04L25/0292
摘要： New very high-speed CMOS techniques are used to achieve a CMOS driver operating at gigabaud speeds. Such a driver may be manufactured more easily than drivers that use GaAs or bipolar techniques and further may be easily integrated with other CMOS circuits. A communication system utilizing the gigabaud CMOS driver may additionally include a receiver with on-chip termination to significantly reduce distortion in the presence of parasitic capacitance in inductance in comparison to a receiver with external termination. Furthermore, the communication system may include a phase tracker and a frame aligner. The phase tracker continously monitors the most frequent transition edges in the oversampled data so that the phase of the receiver clock keeps track of the sender clock. The frame aligner comprises a comma detector which enables instant synchronization of data words with a single comma character within a serial data stream.
摘要翻译：使用新的非常高速的CMOS技术来实现以千兆位速度运行的CMOS驱动器。这样的驱动器可以比使用GaAs或双极技术的驱动器更容易制造，并且还可以容易地与其他CMOS电路集成。与具有外部端接的接收机相比，使用千兆位CMOS驱动器的通信系统可以另外包括具有片上终止的接收器，以在存在电感中的寄生电容的情况下显着减少失真。此外，通信系统可以包括相位跟踪器和帧对准器。相位跟踪器连续监视过采样数据中最频繁的转换边沿，使得接收机时钟的相位跟踪发送器时钟。帧对准器包括逗号检测器，该逗号检测器使串行数据流中具有单个逗号字符的数据字能够即时同步。

3. 发明授权

US07984369B2 Concurrent code checker and hardware efficient high-speed I/O having built-in self-test and debug features 有权
标题翻译：兼容的代码检查器和硬件高效的高速I / O，具有内置的自检和调试功能
公开(公告)号：US07984369B2
公开(公告)日：2011-07-19
申请号：US11656331
申请日：2007-01-19
申请人： Chinsong Sul , Hoon Choi , Gijung Ahn
发明人： Chinsong Sul , Hoon Choi , Gijung Ahn
IPC分类号： G06F11/00 , H03M13/00 , H04L1/00
CPC分类号： H03M5/145 , H03M13/09 , H03M13/6325
摘要： Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a concurrent code checker logic using don't-care conditions, and concurrent code checker circuit having reduce logic element and semiconductor area requirements.
摘要翻译：用于测试高速输入/输出系统中的错误的方法，设备和系统。系统和设备可以包括并发代码检查器，用于通过包括数据包的数据流的数据包静态属性和动态属性来检查编码数据分组中的错误。方法可以涉及使用数据包静态属性和包括数据包的数据流的动态属性检测无效编码包。使用不受保护条件优化并发代码检查器逻辑的设计的方法，以及具有降低逻辑元件和半导体面积要求的并行代码检查器电路的方法。

4. 发明申请

US20050182876A1 Cable with circuitry for asserting stored cable data or other information to an external device or user 有权
标题翻译：电缆，用于将存储的电缆数据或其他信息断言给外部设备或用户
公开(公告)号：US20050182876A1
公开(公告)日：2005-08-18
申请号：US10781405
申请日：2004-02-18
申请人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Kim , Gijung Ahn , Seung Hwang
发明人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Kim , Gijung Ahn , Seung Hwang
IPC分类号： G06F13/00 , G06F13/38
CPC分类号： G06F13/385
摘要： A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.
摘要翻译：包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。电缆可以包括导体，存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路，并且将所访问的数据串行地认定到至少一个导体（例如，用于传输到外部设备）。本发明的其他方面是用于访问存储在电缆中并且可选地使用数据（例如，实现均衡）的电缆数据的方法。电缆数据可以表示电缆类型，等级，速度，长度和阻抗的全部或一些，日期代码，频率相关衰减表，远端串扰和EMI相关系数，共模辐射，内部对歪斜等信息。电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色，亮度和/或闪烁图案的驱动信号的电路。

5. 发明授权

US07269673B2 Cable with circuitry for asserting stored cable data or other information to an external device or user 有权
标题翻译：电缆，用于将存储的电缆数据或其他信息断言给外部设备或用户
公开(公告)号：US07269673B2
公开(公告)日：2007-09-11
申请号：US10781405
申请日：2004-02-18
申请人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Hoon Kim , Gijung Ahn , Seung Ho Hwang
发明人： Ook Kim , Eric Lee , Gyudong Kim , Zeehoon Jang , Baegin Sung , Nam Hoon Kim , Gijung Ahn , Seung Ho Hwang
IPC分类号： G06F13/38
CPC分类号： G06F13/385
摘要： A cable including circuitry for asserting information to a user or external device and a system including such a cable. The cable can include conductors, a memory storing cable data, and circuitry configured to respond to a request received on at least one of the conductors by accessing at least some of the cable data and asserting the accessed data serially to at least one of the conductors (e.g., for transmission to an external device). Other aspects of the invention are methods for accessing cable data stored in a cable and optionally using the data (e.g., to implement equalization). The cable data can be indicative of all or some of cable type, grade, speed, length, and impedance, a date code, a frequency-dependent attenuation table, far-end crosstalk and EMI-related coefficients, common mode radiation, intra pair skew, and other information. The cable can include a radiation-emitting element and circuitry for generating driving signals for causing the radiation-emitting element to produce an appropriate color, brightness, and/or blinking pattern.
摘要翻译：包括用于向用户或外部设备断言信息的电路的电缆以及包括这种电缆的系统。电缆可以包括导体，存储电缆数据的存储器和经配置以通过访问至少一些电缆数据来响应于在至少一个导体上接收到的请求的电路，并且将所访问的数据串行地认定到至少一个导体（例如，用于传输到外部设备）。本发明的其他方面是用于访问存储在电缆中并且可选地使用数据（例如，实现均衡）的电缆数据的方法。电缆数据可以表示电缆类型，等级，速度，长度和阻抗的全部或一些，日期代码，频率相关衰减表，远端串扰和EMI相关系数，共模辐射，内部对歪斜等信息。电缆可以包括辐射发射元件和用于产生用于使辐射发射元件产生适当的颜色，亮度和/或闪烁图案的驱动信号的电路。

6. 发明申请

US20070204204A1 Concurrent code checker and hardware efficient high-speed I/O having built-in self-test and debug features 有权
标题翻译：兼容的代码检查器和硬件高效的高速I / O，具有内置的自检和调试功能
公开(公告)号：US20070204204A1
公开(公告)日：2007-08-30
申请号：US11656331
申请日：2007-01-19
申请人： Chinsong Sul , Hoon Choi , Gijung Ahn
发明人： Chinsong Sul , Hoon Choi , Gijung Ahn
IPC分类号： H03M13/00
CPC分类号： H03M5/145 , H03M13/09 , H03M13/6325
摘要： Method, device, and system for testing for errors in high-speed input/output systems. System and device may include a concurrent code checker for checking for errors in encoded data packets through data packets static properties and dynamic properties of the data stream including the packets. Method may involve detecting invalid encoded packets using the data packets static properties and the dynamic properties of the data stream including the packets. Method for optimizing a design of a concurrent code checker logic using don't-care conditions, and concurrent code checker circuit having reduce logic element and semiconductor area requirements.
摘要翻译：用于测试高速输入/输出系统中的错误的方法，设备和系统。系统和设备可以包括并发代码检查器，用于通过包括数据包的数据流的数据包静态属性和动态属性来检查编码数据分组中的错误。方法可以涉及使用数据包静态属性和包括数据包的数据流的动态属性检测无效编码包。使用不受保护条件优化并发代码检查器逻辑的设计的方法，以及具有降低逻辑元件和半导体面积要求的并行代码检查器电路的方法。

7. 发明授权

US07088398B1 Method and apparatus for regenerating a clock for auxiliary data transmitted over a serial link with video data 有权
标题翻译：用于再生通过串行链路与视频数据传输的辅助数据的时钟的方法和装置
公开(公告)号：US07088398B1
公开(公告)日：2006-08-08
申请号：US10171860
申请日：2002-06-14
申请人： Paul Daniel Wolf , Adrian Sfarti , John D. Banks , Stephen J. Keating , Duane Siemens , Eric Lee , Albert M. Scalise , Gijung Ahn , Seung Ho Hwang , Keewook Jung
发明人： Paul Daniel Wolf , Adrian Sfarti , John D. Banks , Stephen J. Keating , Duane Siemens , Eric Lee , Albert M. Scalise , Gijung Ahn , Seung Ho Hwang , Keewook Jung
IPC分类号： H04N7/08 , H04N7/12 , H04N7/52
CPC分类号： H04L1/0057 , G09G5/006 , H04L1/203 , H04L1/206 , H04L25/49 , H04N5/126 , H04N5/4401 , H04N19/89 , H04N21/233 , H04N21/23602 , H04N21/2368 , H04N21/2383 , H04N21/242 , H04N21/4341 , H04N21/4342
摘要： A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data, a pixel clock is transmitted over the link, and the receiver regenerates a clock for the audio data using time code data in the packets and the pixel clock. Other aspects of the invention are transmitters for transmitting encoded data and a pixel clock over a serial link, receivers for receiving such data and pixel clock and performing audio clock regeneration, and methods for transmitting encoded data and a pixel clock over a serial link and performing clock regeneration using the transmitted data and pixel clock.
摘要翻译：包括发射机，接收机和串行链路的通信系统，其中编码数据（例如，视频，音频，以及可选地还有其他辅助数据）从发射机发射到接收机。串行链接可以但不一定是TMDS或类似TMDS的链接。在典型实施例中，编码音频数据的分组在编码视频数据的脉冲串之间的数据岛期间在链路的一个或多个信道中的每一个上传输，像素时钟通过链路发送，并且接收机重新生成音频数据的时钟使用分组中的时间码数据和像素时钟。本发明的其他方面是用于通过串行链路发射编码数据和像素时钟的发射机，用于接收这种数据和像素时钟并执行音频时钟再生的接收机，以及用于通过串行链路传输编码数据和像素时钟的方法，并执行使用发送的数据和像素时钟进行时钟再生。

8. 发明授权

US06914637B1 Method and system for video and auxiliary data transmission over a serial link 有权
标题翻译：通过串行链路传输视频和辅助数据的方法和系统
公开(公告)号：US06914637B1
公开(公告)日：2005-07-05
申请号：US10192296
申请日：2002-07-10
申请人： Paul Daniel Wolf , John D. Banks , Stephen J. Keating , Duane Siemens , Eric Lee , Albert M. Scalise , Gijung Ahn , Seung Ho Hwang , Keewook Jung , James D. Lyle , Michael Anthony Schumacher , Vladimir Grekhov
发明人： Paul Daniel Wolf , John D. Banks , Stephen J. Keating , Duane Siemens , Eric Lee , Albert M. Scalise , Gijung Ahn , Seung Ho Hwang , Keewook Jung , James D. Lyle , Michael Anthony Schumacher , Vladimir Grekhov
IPC分类号： H04N7/04 , G09G5/00 , H04J3/00 , H04L1/00 , H04L1/20 , H04L25/49 , H04N5/12 , H04N7/045 , H04N19/89 , H04N21/233 , H04N21/236 , H04N21/2368 , H04N21/2383 , H04N21/242 , H04N21/434 , H04N7/52
CPC分类号： H04L1/0057 , G09G5/006 , H04L1/203 , H04L1/206 , H04L25/49 , H04N5/126 , H04N5/4401 , H04N19/89 , H04N21/233 , H04N21/23602 , H04N21/2368 , H04N21/2383 , H04N21/242 , H04N21/4341 , H04N21/4342
摘要： A communication system including a transmitter, a receiver, and a serial link, in which encoded data (e.g., video, audio, and optionally also other auxiliary data) are transmitted from the transmitter to the receiver. The serial link can but need not be a TMDS or TMDS-like link. In typical embodiments, packets of encoded audio data are transmitted over each of one or more channels of the link during data islands between bursts of encoded video data. Other aspects of the invention are transmitters for use in encoding data for transmission over a serial link, receivers for receiving such data, and methods for sending encoded data over a serial link.
摘要翻译：包括发射机，接收机和串行链路的通信系统，其中编码数据（例如，视频，音频，以及可选地还有其他辅助数据）从发射机发射到接收机。串行链接可以但不一定是TMDS或类似TMDS的链接。在典型的实施例中，编码的音频数据的分组在编码的视频数据的脉冲之间的数据岛期间，通过链路的一个或多个信道中的每一个传送。本发明的其他方面是用于编码用于通过串行链路传输的数据的发射机，用于接收这种数据的接收机以及通过串行链路发送编码数据的方法。

9. 发明授权

US08026726B2 Fault testing for interconnections 有权
标题翻译：互连故障测试
公开(公告)号：US08026726B2
公开(公告)日：2011-09-27
申请号：US12359025
申请日：2009-01-23
申请人： Chinsong Sul , Gijung Ahn
发明人： Chinsong Sul , Gijung Ahn
IPC分类号： G01R31/02
CPC分类号： G01R31/31717
摘要： Embodiments of the invention are generally directed to fault testing for interconnections. An embodiment of a fault analysis apparatus includes a test pattern source to provide a test pattern for an interconnection between a transmitter and a receiver, the interconnection having a transmitter end and a receiver end, the interconnection including a first wire and a second wire, the transmitter transmitting the test pattern on the first wire to the receiver. The apparatus further includes a first switch to open and close a first connection for the first wire, and a second switch to open and close a second connection for the second wire. The first switch and the second switch are to be set according to a configuration to set at least a portion of a test path for the detection of one or more faults in the interconnection.
摘要翻译：本发明的实施例一般涉及互连的故障测试。故障分析装置的实施例包括测试模式源，以提供用于发射器和接收器之间的互连的测试模式，所述互连具有发射器端和接收器端，所述互连包括第一线和第二线，发射机将测试图案发送到接收机。该装置还包括用于打开和闭合用于第一线的第一连接的第一开关和用于打开和闭合第二线的第二连接的第二开关。根据配置设置第一开关和第二开关以设置用于检测互连中的一个或多个故障的测试路径的至少一部分。

10. 发明申请

US20100188097A1 FAULT TESTING FOR INTERCONNECTIONS 有权
标题翻译：互连故障测试
公开(公告)号：US20100188097A1
公开(公告)日：2010-07-29
申请号：US12359025
申请日：2009-01-23
申请人： Chinsong Sul , Gijung Ahn
发明人： Chinsong Sul , Gijung Ahn
IPC分类号： G01R31/02 , G01R31/00
CPC分类号： G01R31/31717
摘要： Embodiments of the invention are generally directed to fault testing for interconnections. An embodiment of a fault analysis apparatus includes a test pattern source to provide a test pattern for an interconnection between a transmitter and a receiver, the interconnection having a transmitter end and a receiver end, the interconnection including a first wire and a second wire, the transmitter transmitting the test pattern on the first wire to the receiver. The apparatus further includes a first switch to open and close a first connection for the first wire, and a second switch to open and close a second connection for the second wire. The first switch and the second switch are to be set according to a configuration to set at least a portion of a test path for the detection of one or more faults in the interconnection.
摘要翻译：本发明的实施例一般涉及互连的故障测试。故障分析装置的实施例包括测试模式源，以提供用于发射器和接收器之间的互连的测试模式，所述互连具有发射器端和接收器端，所述互连包括第一线和第二线，发射机将测试图案发送到接收机。该装置还包括用于打开和闭合用于第一线的第一连接的第一开关和用于打开和闭合第二线的第二连接的第二开关。根据配置设置第一开关和第二开关以设置用于检测互连中的一个或多个故障的测试路径的至少一部分。

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