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1. 发明授权

US06870930B1 Methods and systems for TMDS encryption 有权
标题翻译： TMDS加密的方法和系统
公开(公告)号：US06870930B1
公开(公告)日：2005-03-22
申请号：US09579811
申请日：2000-05-26
申请人： Gyudong Kim , Victor M. Da Costa , Bruce Kim , David D. Lee , Russel A. Martin , Seung Ho Hwang
发明人： Gyudong Kim , Victor M. Da Costa , Bruce Kim , David D. Lee , Russel A. Martin , Seung Ho Hwang
IPC分类号： H04L9/08 , H04L9/12 , H04L9/18 , H04N7/167 , H04N7/173 , H04L9/00 , H04K1/06
CPC分类号： G09G5/006 , H04L9/065 , H04L9/0844 , H04L9/12 , H04L2209/046 , H04L2209/34 , H04L2209/605 , H04N7/1675 , H04N7/17318 , H04N21/23476 , H04N21/44055 , H04N21/63345
摘要： The present invention is directed to systems and methods for protecting digital content during transmission. One version of the invention provides a method for encryption in a high-speed digital video transmission system that includes the steps of: a) performing transition controlled encoding of a first sequence of n bit data words into encoded n+1 bit data characters where the n is a positive integer, b) performing XOR masking of the encoded n+1 bit data characters with an XOR mask to produce masked n+1 bit data characters; c) DC balancing the masked n+1 bit data characters to produce DC balanced, masked n+2 bit data characters; d) scrambling the DC balanced, masked n+2 bit data characters using a scrambling formula to produce encrypted n+2 bit data characters; e) encoding control data into encoded n+2 bit control characters, f) generating a serial data stream in response to the encrypted data characters and encoded control characters, and g) transmitting the serial data stream over a communication link. Subsequent to step (e) and prior to step (f), the method can further include the step of encrypting the encoded n+2 bit control characters, such that the generating step generates a serial data stream in response to the encrypted data characters and the encrypted control characters.
摘要翻译：本发明涉及用于在传输期间保护数字内容的系统和方法。本发明的一个方案提供了一种用于在高速数字视频传输系统中进行加密的方法，该方法包括以下步骤：a）对n位数据字的第一序列进行转换控制编码，以编码到编码的n + 1位数据字符中，其中 n是正整数，b）用XOR掩码执行编码的n + 1位数据字符的异或掩蔽，以产生掩蔽的n + 1位数据字符; c）直流平衡屏蔽的n + 1位数据字符，以产生直流平衡，屏蔽的n + 2位数据字符; d）使用扰频公式对DC平衡掩蔽的n + 2位数据字符进行加扰，以产生加密的n + 2位数据字符; e）将控制数据编码为编码的n + 2位控制字符，f）响应于加密的数据字符和编码的控制字符产生串行数据流，以及g）通过通信链路发送串行数据流。在步骤（e）之后和步骤（f）之后，该方法还可以包括对编码的n + 2位控制字符进行加密的步骤，使得生成步骤响应于加密的数据字符生成串行数据流，并且加密的控制字符。

2. 发明授权

US06961095B2 Digital display jitter correction apparatus and method 有权
标题翻译：数字显示抖动校正装置及方法
公开(公告)号：US06961095B2
公开(公告)日：2005-11-01
申请号：US09922990
申请日：2001-08-03
申请人： Stephen J. Keating , Russel A. Martin , Victor M. Da Costa , Gyudong Kim
发明人： Stephen J. Keating , Russel A. Martin , Victor M. Da Costa , Gyudong Kim
IPC分类号： H03K5/13 , H04L7/02 , H04N5/208 , H04N5/21 , H04N9/64
CPC分类号： H04L7/02 , H04N5/208 , H04N5/21
摘要： A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the jitter corrected falling edge, and to output a jitter corrected signal.
摘要翻译：公开了一种抖动校正装置和方法。在一个实施例中，该装置具有上升沿校正器以接收抖动信号并输出抖动信号的抖动校正上升沿。该装置还可以具有下降沿校正器以接收抖动信号并输出抖动信号的抖动校正下降沿。抖动校正装置可以包括用于接收抖动校正的上升沿，接收抖动校正的下降沿并输出抖动校正信号的输出装置。

3. 发明授权

US07557863B2 Digital display jitter correction apparatus and method 有权
公开(公告)号：US07557863B2
公开(公告)日：2009-07-07
申请号：US11219323
申请日：2005-09-01
申请人： Stephen J. Keating , Russel Martin , Victor M. Da Costa , Gyudong Kim
发明人： Stephen J. Keating , Russel Martin , Victor M. Da Costa , Gyudong Kim
IPC分类号： H04N9/64 , G06K19/06
CPC分类号： H04L7/02 , H04N5/208 , H04N5/21
摘要： A jitter correction apparatus and method are disclosed. In one embodiment, the apparatus has a rising edge corrector to receive a jittered signal and to output a jitter corrected rising edge of the jittered signal. The apparatus may also have a falling edge corrector to receive the jittered signal and to output a jitter corrected falling edge of the jittered signal. The jitter correction apparatus may include an output device to receive the jitter corrected rising edge, to receive the jitter corrected falling edge, and to output a jitter corrected signal.

4. 发明授权

US6100879A System and method for controlling an active matrix display 失效
标题翻译：用于控制有源矩阵显示的系统和方法
公开(公告)号：US6100879A
公开(公告)日：2000-08-08
申请号：US909022
申请日：1997-08-11
申请人： Victor M. Da Costa
发明人： Victor M. Da Costa
IPC分类号： G09G3/20 , G09G3/36 , G09G5/00
CPC分类号： G09G3/3696 , G09G3/3648 , G09G2310/027 , G09G2320/0276 , G09G2320/041 , G09G2370/04 , G09G3/2011
摘要： A smart controller chip for controlling an active matrix display. Within the controller chip, circuitry for generating analog reference levels is incorporated alongside circuitry for generating digital timing and control signals. The combination of D/A analog circuitry and standard digital logic makes the controller uniquely suited for addressing all the panel control needs both for the normal digital functions but also for control of the analog aspects of the panel, like display gamma. The analog reference levels and the digital signals are made programmable using registers internal to the controller chip. The contents of these registers are programmed initially by digital values stored in an external PROM or in flash memory integrated into the controller chip. In addition, software in a host system is able to program these registers via an interface between the host system and the controller chip.
摘要翻译：用于控制有源矩阵显示的智能控制器芯片。在控制器芯片内，用于产生模拟参考电平的电路与用于产生数字定时和控制信号的电路并入。 D / A模拟电路和标准数字逻辑的组合使得控制器非常适合寻址正常数字功能的所有面板控制需求，也可用于控制面板的模拟方面，如显示伽玛。模拟参考电平和数字信号使用控制器芯片内部的寄存器进行编程。这些寄存器的内容最初由存储在外部PROM中的数字值或集成到控制器芯片中的闪存中进行编程。此外，主机系统中的软件能够通过主机系统和控制器芯片之间的接口对这些寄存器进行编程。

5. 发明授权

US5073723A Space charge current limited shunt in a cascode circuit for HVTFT devices 失效
标题翻译：空中充电电流有限公司在用于HVTFT设备的CASCODE电路中
公开(公告)号：US5073723A
公开(公告)日：1991-12-17
申请号：US565767
申请日：1990-08-10
申请人： Victor M. Da Costa
发明人： Victor M. Da Costa
IPC分类号： H03K17/04 , H03K17/10 , H03K17/687 , H03K17/693
CPC分类号： H03K17/693 , H03K17/102 , H03K17/6871
摘要： A cascode circuit for switching a high voltage thin film transistor substantially over its entire high voltage range, comprising a leaky low voltage thin film transistor connected in series with the high voltage thin film transistor, the transistors being connected between a source of high potential and a source of reference potential, and the leaky low voltage thin film transistor includes a space charge limited current shunt connected in parallel with the low voltage thin film transistor.

6. 发明授权

US5166960A Parallel multi-phased a-Si shift register for fast addressing of an a-Si array 失效
标题翻译：并联多相a-Si移位寄存器，用于快速寻址a-Si阵列
公开(公告)号：US5166960A
公开(公告)日：1992-11-24
申请号：US871243
申请日：1992-04-20
申请人： Victor M. Da Costa
发明人： Victor M. Da Costa
IPC分类号： G11C19/00 , G11C8/04 , G11C19/28 , H03K19/173
CPC分类号： G11C8/04 , G11C19/28 , H03K19/1732
摘要： An improved shift register assembly having an integrated multi-phased dynamic shift register with a corresponding multi-phased driving buffer for addressing elements of an array. The shift register and buffer combination is used to select segments on the array having a common select line thus reducing the number of input lines needed to address such an array. Furthermore, the multi-phased operation of the shift register allows for faster operation than tyhat of a traditional shift register setup.
摘要翻译：一种改进的移位寄存器组件，其具有集成的多相动态移位寄存器，其具有用于寻址阵列元件的对应的多相驱动缓冲器。移位寄存器和缓冲器组合用于选择具有公共选择线的阵列上的段，从而减少了解决这种阵列所需的输入线的数量。此外，移位寄存器的多阶段操作允许比传统移位寄存器设置的tyhat更快的操作。

7. 发明授权

US5237346A Integrated thin film transistor electrographic writing head 失效
标题翻译：集成薄膜晶体管电子书写头
公开(公告)号：US5237346A
公开(公告)日：1993-08-17
申请号：US871250
申请日：1992-04-20
申请人： Victor M. Da Costa , Patrick A. O'Connell
发明人： Victor M. Da Costa , Patrick A. O'Connell
IPC分类号： B41J2/385 , G06K15/14 , H04N1/032
CPC分类号： G06K15/14
摘要： An integrated thin film electrographic writing head. The writing head has integrated therein a plurality of marking electrodes or nibs arranged in a linear array for writing onto a medium, and a plurality of high voltage driving circuits for driving the nibs. The write head also includes a plurality of latches each connected to the high voltage driving circuits, a plurality of memory cells each connected to the latches, a plurality of buffers, each buffer supplying a select line to the plurality of memory cells, and a plurality of selection elements, supplying a selection signal to each of the buffers to drive a segment of memory cells. The integrated memory means and latching means allow for simultaneous latching and writing of an entire scanline of data.
摘要翻译：一体的薄膜电子书写头。写入头在其中集成有多个标记电极或笔尖，其布置成线性阵列以便写入介质，以及多个用于驱动笔尖的高压驱动电路。写头还包括多个锁存器，每个锁存器均连接到高电压驱动电路，多个存储器单元，每个存储器单元各自连接到锁存器，多个缓冲器，每个缓冲器向多个存储器单元提供选择线，以及多个的选择元件，将选择信号提供给每个缓冲器以驱动一段存储器单元。集成存储器装置和锁存装置允许同时锁存和写入数据的整个扫描线。

8. 发明授权

US5105246A Leaky low voltage thin film transistor 失效
标题翻译：漏电低压薄膜晶体管
公开(公告)号：US5105246A
公开(公告)日：1992-04-14
申请号：US566015
申请日：1990-08-10
申请人： Victor M. Da Costa
发明人： Victor M. Da Costa
IPC分类号： H01L27/13
CPC分类号： H01L27/13
摘要： A leaky thin film transistor including a charge transport layer, source and drain electrodes located adjacent to the charge transport layer, a gate electrode spaced from the charge transport layer by a gate dielectric layer, the gate electrode defining a gated portion of the charge transport layer extending between the source electrode and the drain electrode, and an ungated portion of the charge transport layer extending between the source and drain electrodes and providing an electrical path for leakage current to flow between the source and drain electrodes in parallel with the gated path between the source and drain electrodes.
摘要翻译：一种泄漏的薄膜晶体管，包括电荷输送层，位于电荷输送层附近的源电极和漏电极，栅电极通过栅介质层与电荷输送层隔开，栅电极限定电荷输送层的门控部分在源电极和漏电极之间延伸，以及电荷输送层的未选择部分在源电极和漏电极之间延伸，并且提供用于泄漏电流在电源和漏电极之间平行流动的电路径，源极和漏极。

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