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    • 5. 发明申请
    • ERROR DETECTION AND CORRECTION IN SEMICONDUCTOR STRUCTURES
    • 半导体结构中的错误检测和校正
    • US20070241398A1
    • 2007-10-18
    • US11277306
    • 2006-03-23
    • Timothy DaltonMarc FaucherPaul KartschokePeter Sandon
    • Timothy DaltonMarc FaucherPaul KartschokePeter Sandon
    • H01L27/12H01L27/01H01L31/0392
    • H01L25/0657G01R31/318513H01L2225/06513H01L2225/06596H01L2924/0002H01L2924/00
    • A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.
    • 半导体结构及其操作方法。 半导体结构包括第一半导体芯片和第二半导体芯片。 第一半导体芯片位于第二半导体芯片的顶部并结合到第二半导体芯片上。 第一和第二半导体芯片包括第一和第二电节点。 第二半导体芯片还包括第一比较电路。 半导体结构还包括通过将第一半导体芯片的第一电节点电连接到第二半导体芯片的第一比较电路的第一耦合。 第一比较电路能够(i)直接从第二电节点接收输入信号,(ii)通过第一耦合通路间接接收来自第一电节点的输入信号,以及(iii)将第一不匹配信号置于 对来自第一和第二电节点的输入信号的响应是不同的。
    • 8. 发明申请
    • Multiple Layer Resist Scheme Implementing Etch Recipe Particular to Each Layer
    • 多层抗扰性方案实现每层专用的蚀刻配方
    • US20060094230A1
    • 2006-05-04
    • US10904323
    • 2004-11-04
    • Nicholas FullerTimothy DaltonRaymond JoyYi-hsiung LinChun Low
    • Nicholas FullerTimothy DaltonRaymond JoyYi-hsiung LinChun Low
    • H01L21/4763
    • H01L21/76802H01L21/0332H01L21/31138H01L21/31144
    • Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.
    • 公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸(CD)的方法和实现的抗蚀剂方案。 该方法包括形成多层抗蚀剂方案,该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层,平坦化层上的第二类型材料的第二电介质层,以及在电介质上的第三类型材料的第三光致抗蚀剂层 层。 有机材料和无机材料之间的材料类型是交替的。 第三层被图案化为金属线和/或经由CD。 然后使用对每一个被暴露的第一光致抗蚀剂层,第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。 提供准确的CD形成和足够的抗蚀剂预算。
    • 10. 发明申请
    • Formation of low resistance via contacts in interconnect structures
    • 通过互连结构中的触点形成低电阻
    • US20050266681A1
    • 2005-12-01
    • US11182445
    • 2005-07-15
    • Timothy DaltonStephen Gates
    • Timothy DaltonStephen Gates
    • H01L21/306H01L21/311H01L21/768H01L21/4763
    • H01L21/02063H01L21/76814
    • A method of fabricating BEOL interconnect structures on a semiconductor device having a plurality of via contacts with low via contact resistance is provided. The method includes the steps of: a) forming a porous or dense low k dielectric layer on a substrate; b) forming single or dual damascene etched openings in the low k dielectric; c) placing the substrate in a process chamber on a cold chuck at a temperature about −200° C. to about 25° C.; d) adding to the process chamber a condensable cleaning agent (CCA) to condense a layer of CCA within the etched openings on the substrate; and e) performing an activation step while the wafer remains cold at a temperature of about −200° C. to about 25° C. The via contacts are very stable during thermal cycles and during operation of the semiconductor device.
    • 提供了在具有多个通孔接触电阻低的半导体器件上制造BEOL互连结构的方法。 该方法包括以下步骤:a)在衬底上形成多孔或致密的低k电介质层; b)在低k电介质中形成单个或双镶嵌蚀刻开口; c)将基板放置在约-200℃至约25℃的温度下的冷卡盘上的处理室中; d)向处理室中加入可冷凝清洁剂(CCA),以在衬底上的蚀刻开口内冷凝CCA层; 以及e)当晶片在约-200℃至约25℃的温度下保持冷时,执行激活步骤。在热循环期间和在半导体器件的操作期间,通孔触点是非常稳定的。