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1. 发明申请

US20080091759A1 METHOD OF COMPUTING PARTIAL CRCS 失效
标题翻译：计算部分CRCS的方法
公开(公告)号：US20080091759A1
公开(公告)日：2008-04-17
申请号：US11937204
申请日：2007-11-08
申请人： Richard ANDERSON , Christos Georgiou , Peter Sandon
发明人： Richard ANDERSON , Christos Georgiou , Peter Sandon
IPC分类号： G06F7/44
CPC分类号： H04L1/0041 , H03M13/09 , H03M13/091 , H03M13/093 , H03M13/6516 , H04L1/0061
摘要： Apparatus and method of generating cyclic redundancy checks (CRCs) for a message with N data blocks. The method includes calculating a partial CRC for an out of order data block and storing the result, generating, using a division operation, a CRC remainder multiplier associated with the out of order data block and storing the result, repeating the calculating and generating steps until all N data blocks for the message are received; and combining the results of the calculating step and the generating step.
摘要翻译：为具有N个数据块的消息生成循环冗余校验（CRC）的装置和方法。该方法包括计算一个无序数据块的部分CRC并存储该结果，使用除法运算产生与该次序数据块相关联的CRC余数乘数并存储该结果，重复该计算和生成步骤直到接收消息的所有N个数据块; 并结合计算步骤和生成步骤的结果。

2. 发明申请

US20070241398A1 ERROR DETECTION AND CORRECTION IN SEMICONDUCTOR STRUCTURES 有权
标题翻译：半导体结构中的错误检测和校正
公开(公告)号：US20070241398A1
公开(公告)日：2007-10-18
申请号：US11277306
申请日：2006-03-23
申请人： Timothy Dalton , Marc Faucher , Paul Kartschoke , Peter Sandon
发明人： Timothy Dalton , Marc Faucher , Paul Kartschoke , Peter Sandon
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L25/0657 , G01R31/318513 , H01L2225/06513 , H01L2225/06596 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method for operating the same. The semiconductor structure includes a first semiconductor chip and a second semiconductor chip. The first semiconductor chip is on top of and bonded to the second semiconductor chip. The first and second semiconductor chips include a first and a second electric nodes. The second semiconductor chip further includes a first comparing circuit. The semiconductor structure further includes a first coupling via electrically connecting the first electric node of the first semiconductor chip to the first comparing circuit of the second semiconductor chip. The first comparing circuit is capable of (i) receiving an input signal from the second electric node directly, (ii) receiving an input signal from the first electric node indirectly through the first coupling via, and (iii) asserting a first mismatch signal in response to the input signals from the first and second electric nodes being different.
摘要翻译：半导体结构及其操作方法。半导体结构包括第一半导体芯片和第二半导体芯片。第一半导体芯片位于第二半导体芯片的顶部并结合到第二半导体芯片上。第一和第二半导体芯片包括第一和第二电节点。第二半导体芯片还包括第一比较电路。半导体结构还包括通过将第一半导体芯片的第一电节点电连接到第二半导体芯片的第一比较电路的第一耦合。第一比较电路能够（i）直接从第二电节点接收输入信号，（ii）通过第一耦合通路间接接收来自第一电节点的输入信号，以及（iii）将第一不匹配信号置于对来自第一和第二电节点的输入信号的响应是不同的。

3. 发明申请

US20060064606A1 A METHOD AND APPARATUS FOR CONTROLLING POWER CONSUMPTION IN AN INTEGRATED CIRCUIT 审中-公开
标题翻译：一种用于控制集成电路中的功耗的方法和装置
公开(公告)号：US20060064606A1
公开(公告)日：2006-03-23
申请号：US10711485
申请日：2004-09-21
申请人： Suhwan Kim , Stephen Kosonocky , Peter Sandon
发明人： Suhwan Kim , Stephen Kosonocky , Peter Sandon
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3243 , G06F1/3293 , Y02D10/122 , Y02D10/126 , Y02D10/152
摘要： A method and apparatus for controlling power consumption by devices in an integrated circuit. The apparatus includes a complementary device for a corresponding device for which power consumption is desired to be reduced. The complementary device supports all or some of the tasks of the corresponding device. The complementary device receives tasks that can be executed by either itself or the corresponding device and based upon the power management scheme will either execute the task itself or allow the corresponding device.
摘要翻译：一种用于控制集成电路中的器件的功耗的方法和装置。该装置包括用于相应设备的补充设备，期望降低功耗。互补设备支持相应设备的全部或部分任务。互补设备接收可以由其自身或相应设备执行的任务，并且基于功率管理方案将执行任务本身或允许相应的设备。

4. 发明申请

US20060009952A1 Method of computing partial CRCs 失效
标题翻译：部分CRC的计算方法
公开(公告)号：US20060009952A1
公开(公告)日：2006-01-12
申请号：US11224994
申请日：2005-09-14
申请人： Richard Anderson , Christos Georgiou , Peter Sandon
发明人： Richard Anderson , Christos Georgiou , Peter Sandon
IPC分类号： G06F17/00
CPC分类号： H04L1/0041 , H03M13/09 , H03M13/091 , H03M13/093 , H03M13/6516 , H04L1/0061
摘要： Method of generating cyclic redundancy checks (CRCS) for a message with N data blocks. The method includes calculating a partial CRC for an out of order data block and storing the result, generating, using a division operation, a CRC remainder multiplier associated with the out of order data block and storing the result, repeating the calculating and generating steps until all N data blocks for the message are received, and combining the results of the calculating step and the generating step.
摘要翻译：为具有N个数据块的消息生成循环冗余校验（CRCS）的方法。该方法包括计算一个无序数据块的部分CRC并存储该结果，使用除法运算产生与该次序数据块相关联的CRC余数乘数并存储该结果，重复该计算和生成步骤直到接收消息的所有N个数据块，并将计算步骤的结果与生成步骤进行组合。

5. 发明申请

US20050104637A1 SYSTEM AND METHOD FOR SYNCHRONIZING DIVIDE-BY COUNTERS 失效
标题翻译：同步计数器的系统和方法
公开(公告)号：US20050104637A1
公开(公告)日：2005-05-19
申请号：US10707066
申请日：2003-11-19
申请人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Mathew Ringler , Gerard Salem , Peter Sandon , Dana Thygesen , Ulrich Weiss
发明人： Rolf Hilgendorf , Jens Kuenzer , Cedric Lichtenau , Thomas Pflueger , Mathew Ringler , Gerard Salem , Peter Sandon , Dana Thygesen , Ulrich Weiss
IPC分类号： H03L7/06
CPC分类号： H03L7/06
摘要： A synchronization system capable of simultaneously resetting frequency divide-by counters (124A, 124B) of multiple processors (A, B) to zero regardless of the divide-by frequency signal (Mclk/n signal (168A, 168B)) and regardless of the magnitude of the clock mesh delays experienced by the Mclk/n signals in the processors. The synchronization system includes a mesh delay circuit (176A, 176B) for each processor that simulates in the undivided signal (Mclk/1 signal (136A, 136B)) the clock mesh delay experienced by the Mclk/n signal in that processor so as to provide an Lclk signal (172A, 172B). A phase detector detects the phase offset between the Mclk/n signal and the Sysclk signal (112) and sends an asynchronous offset signal (194A, 194B) to a counter re-setter (196A, 196B) that resets the divide-by counter to zero based on the offset signal.
摘要翻译：能够将多个处理器（A，B）的频率分频计数器（124A，124BB）同时复位的同步系统为零，而不管分频频率信号（Mclk / n信号（168A，168B）），并且与处理器中的Mclk / n信号经历的时钟网格延迟的大小无关。同步系统包括用于在未分割信号中模拟的每个处理器的网格延迟电路（176A，176BB）（Mclk / 1信号（136 < / SUB>，136 B））由该处理器中的Mclk / n信号经历的时钟网格延迟，以便提供Lclk信号（172 ，172 _{B ）。相位检测器检测Mclk / n信号和Sysclk信号之间的相位偏移（112），并将异步偏移信号（194A，192B）发送到计数器基于偏移信号将再分配计数器复位为零的重新设置器（196A，196BB）。}

6. 发明申请

US20080278195A1 STRUCTURE FOR EXECUTING SOFTWARE WITHIN REAL-TIME HARDWARE CONSTRAINTS USING FUNCTIONALLY PROGRAMMABLE BRANCH TABLE 审中-公开
标题翻译：使用功能可编程分支表在实时硬件约束中执行软件的结构
公开(公告)号：US20080278195A1
公开(公告)日：2008-11-13
申请号：US12118234
申请日：2008-05-09
申请人： Kenneth Goodnow , Todd Edwin Leonard , Jason M. Norman , Clarence Ross Ogilvie , Peter Sandon , Charles Woodruff
发明人： Kenneth Goodnow , Todd Edwin Leonard , Jason M. Norman , Clarence Ross Ogilvie , Peter Sandon , Charles Woodruff
IPC分类号： H03K19/173
CPC分类号： G06F17/5027
摘要： A computer system is disclosed which includes a design structure including a CPU or microprocessor to drive tightly constrained hardware events. The system comprises a processor having a set of system inputs to drive a functionally programmable event, and a fast branch in the CPU including a state handler to execute instructions from the CPU to process the event. A queue in the CPU stores the events such that the non-pre-empted events are serviced in the order they are received.
摘要翻译：公开了一种计算机系统，其包括包括用于驱动紧密约束的硬件事件的CPU或微处理器的设计结构。该系统包括具有用于驱动功能可编程事件的一组系统输入的处理器，以及CPU中的快速分支，包括状态处理程序，以执行来自CPU的处理该事件的指令。 CPU中的队列存储事件，使得非预先占用的事件按照接收的顺序进行服务。

7. 发明申请

US20070208964A1 METHOD AND APPARATUS FOR DYNAMIC SYSTEM-LEVEL FREQUENCY SCALING 失效
标题翻译：用于动态系统级频率范围的方法和装置
公开(公告)号：US20070208964A1
公开(公告)日：2007-09-06
申请号：US10595520
申请日：2003-10-31
申请人： Peter Sandon , Cedric Lichtenau , Martin Recktenwald , Thomas Pflueger , Rolf Hilgendorf
发明人： Peter Sandon , Cedric Lichtenau , Martin Recktenwald , Thomas Pflueger , Rolf Hilgendorf
IPC分类号： G06F1/08
CPC分类号： H03L7/16 , G06F1/08
摘要： A method and apparatus for changing a clock frequency in a system (10) comprising a plurality of synchronous integrated circuit chips (12, 14, 16), and a circuit (20) for implementing the frequency change. The method includes: detecting a change in processing requirements in one of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that a clock frequency change is to occur; achieving a quiescent bus state in each of the plurality of synchronous integrated circuit chips; notifying the plurality of synchronous integrated circuit chips that the clock frequency change can occur; and changing the clock frequency of the plurality of integrated circuit chips.
摘要翻译：一种用于改变包括多个同步集成电路芯片（12,14,16）的系统（10）中的时钟频率的方法和装置，以及用于实现频率变化的电路（20）。该方法包括：检测多个同步集成电路芯片之一中处理要求的变化; 通知多个同步集成电路芯片发生时钟频率变化; 在所述多个同步集成电路芯片的每一个中实现静态总线状态; 通知多个同步集成电路芯片可能发生时钟频率变化; 以及改变多个集成电路芯片的时钟频率。

8. 发明申请

US20050021926A1 Method and apparatus for efficient loading and storing of vectors 有权
标题翻译：用于有效加载和存储载体的方法和装置
公开(公告)号：US20050021926A1
公开(公告)日：2005-01-27
申请号：US10849804
申请日：2004-05-21
申请人： Yu-Chung Liao , Peter Sandon , Howard Cheng
发明人： Yu-Chung Liao , Peter Sandon , Howard Cheng
IPC分类号： G06F17/16 , G06F9/302 , G06F9/312 , G06F15/00
CPC分类号： G06F9/30145 , G06F9/30014 , G06F9/30025 , G06F9/30036 , G06F9/30043 , G06F9/30109 , G06F9/30167
摘要： A method and apparatus for loading and storing vectors from and to memory, including embedding a location identifier in bits comprising a vector load and store instruction, wherein the location identifier indicates a location in the vector where useful data ends. The vector load instruction further includes a value field that indicates a particular constant for use by the load/store unit to set locations in the vector register beyond the useful data with the constant. By embedding the ending location of the useful date in the instruction, bandwidth and memory are saved by only requiring that the useful data in the vector be loaded and stored.
摘要翻译：一种用于从存储器加载和存储向量的方法和装置，包括在包括向量加载和存储指令的位中嵌入位置标识符，其中所述位置标识符指示所述向量中的有用数据结束的位置。向量加载指令还包括值字段，其指示加载/存储单元使用的特定常数，以将矢量寄存器中的位置设置为超过具有常数的有用数据。通过将有用日期的结束位置嵌入指令中，只需要加载和存储向量中的有用数据即可保存带宽和存储器。

9. 发明申请

US20080098200A1 TWO DIMENSIONAL ADDRESSING OF A MATRIX-VECTOR REGISTER ARRAY 有权
标题翻译：矩阵矢量寄存器阵列的二维寻址
公开(公告)号：US20080098200A1
公开(公告)日：2008-04-24
申请号：US11950474
申请日：2007-12-05
申请人： Peter Sandon , R. Michael West
发明人： Peter Sandon , R. Michael West
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/3012 , G06F9/3001 , G06F9/30032 , G06F9/30043 , G06F9/30109 , G06F9/30145 , G06F15/8084
摘要： A processor for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N≧2, M≧2, K≧2, and B≧1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.
摘要翻译：用于处理矩阵数据的处理器。处理器包括M个独立的向量寄存器文件，其适于集中地存储L个数据元素的矩阵。每个数据元素都有B位二进制位。矩阵具有N行和M列，L = N * M。每列有K个子列。 N> = 2，M> = 2，K> = 2，B> = 1。每行和每个子列都是可寻址的。处理器不会重复存储L个数据元素。矩阵包括一组阵列，使得每个数组是矩阵的行或子列。处理器可以执行对该组阵列的第一阵列执行操作的指令，使得以相对于第一阵列的数据元素的选择性执行该操作。

10. 发明申请

US20080046681A1 TWO DIMENSIONAL ADDRESSING OF A MATRIX-VECTOR REGISTER ARRAY 有权
标题翻译：矩阵矢量寄存器阵列的二维寻址
公开(公告)号：US20080046681A1
公开(公告)日：2008-02-21
申请号：US11850920
申请日：2007-09-06
申请人： Peter Sandon , R. Michael West
发明人： Peter Sandon , R. Michael West
IPC分类号： G06F15/00
CPC分类号： G06F9/3012 , G06F9/3001 , G06F9/30032 , G06F9/30043 , G06F9/30109 , G06F9/30145 , G06F15/8084
摘要： A processor and method for processing matrix data. The processor includes M independent vector register files which are adapted to collectively store a matrix of L data elements. Each data element has B binary bits. The matrix has N rows and M columns, and L=N*M. Each column has K subcolumns. N≧2, M≧2, K≧2, and B≧1. Each row and each subcolumn is addressable. The processor does not duplicatively store the L data elements. The matrix includes a set of arrays such that each array is a row or subcolumn of the matrix. The processor may execute an instruction that performs an operation on a first array of the set of arrays, such that the operation is performed with selectivity with respect to the data elements of the first array.
摘要翻译：一种用于处理矩阵数据的处理器和方法。处理器包括M个独立的向量寄存器文件，其适于集中地存储L个数据元素的矩阵。每个数据元素都有B位二进制位。矩阵具有N行和M列，L = N * M。每列有K个子列。 N> = 2，M> = 2，K> = 2，B> = 1。每行和每个子列都是可寻址的。处理器不会重复存储L个数据元素。矩阵包括一组阵列，使得每个数组是矩阵的行或子列。处理器可以执行对该组阵列的第一阵列执行操作的指令，使得以相对于第一阵列的数据元素的选择性执行该操作。

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