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1. 发明申请

US20060094230A1 Multiple Layer Resist Scheme Implementing Etch Recipe Particular to Each Layer 有权
标题翻译：多层抗扰性方案实现每层专用的蚀刻配方
公开(公告)号：US20060094230A1
公开(公告)日：2006-05-04
申请号：US10904323
申请日：2004-11-04
申请人： Nicholas Fuller , Timothy Dalton , Raymond Joy , Yi-hsiung Lin , Chun Low
发明人： Nicholas Fuller , Timothy Dalton , Raymond Joy , Yi-hsiung Lin , Chun Low
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/0332 , H01L21/31138 , H01L21/31144
摘要： Methods of forming a metal line and/or via critical dimension (CD) in a single or dual damascene process on a semiconductor substrate, and the resist scheme implemented, are disclosed. The method includes forming a multiple layer resist scheme including a first planarizing layer of a first type material over the substrate, a second dielectric layer of a second type material over the planarizing layer, and a third photoresist layer of a third type material over the dielectric layer. The types of material alternate between organic and inorganic material. The third layer is patterned for the metal line and/or via CD. Sequential etching to form the metal line and/or via critical dimension using a tailored etch recipe particular to each of the first photoresist layer, the second dielectric layer and the third planarizing layer as each layer is exposed is then used. Accurate CD formation and adequate resist budget are provided.
摘要翻译：公开了在半导体衬底上的单镶嵌或双镶嵌工艺中形成金属线和/或通过临界尺寸（CD）的方法和实现的抗蚀剂方案。该方法包括形成多层抗蚀剂方案，该多层抗蚀剂方案包括在该衬底上的第一类型材料的第一平坦化层，平坦化层上的第二类型材料的第二电介质层，以及在电介质上的第三类型材料的第三光致抗蚀剂层层。有机材料和无机材料之间的材料类型是交替的。第三层被图案化为金属线和/或经由CD。然后使用对每一个被暴露的第一光致抗蚀剂层，第二介电层和第三平坦化层中的每一个特定的定制蚀刻配方进行顺序蚀刻以形成金属线和/或通过临界尺寸。提供准确的CD形成和足够的抗蚀剂预算。

2. 发明申请

US20060160354A1 Via electromigration improvement by changing the via bottom geometric profile 有权
公开(公告)号：US20060160354A1
公开(公告)日：2006-07-20
申请号：US11374848
申请日：2006-03-14
申请人： BeiChao Zhang , Chun Low , Hong Lee , Sang Loong , Qiang Guo
发明人： BeiChao Zhang , Chun Low , Hong Lee , Sang Loong , Qiang Guo
IPC分类号： H01L21/4763
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.

3. 发明申请

US20050090097A1 Via electromigration improvement by changing the via bottom geometric profile 有权
标题翻译：通过改变通孔底部几何轮廓来改善电迁移
公开(公告)号：US20050090097A1
公开(公告)日：2005-04-28
申请号：US10692028
申请日：2003-10-23
申请人： Beichao Zhang , Chun Low , Hong Lee , Sang Loong , Giang Guo
发明人： Beichao Zhang , Chun Low , Hong Lee , Sang Loong , Giang Guo
IPC分类号： H01L21/4763 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/76805 , H01L21/76814
摘要： An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion barrier layer and a second metal layer. A key feature is that the etch process can be selected to vary the shape and location of the via bottom. A round or partially rounded bottom is formed in the first metal layer to reduce mechanical stress near the diffusion barrier layer. On the other hand, a flat bottom which stops on or in the TiN ARC is selected when exposure of the first metal layer to subsequent processing steps is a primary concern. Electromigration resistance is found to be lower than for a via structure with a flat bottom formed in a first metal layer.
摘要翻译：描述了一种用于提高半导体器件中的电迁移阻力的集成方法。在包括上电介质层，中间TiN ARC和下第一金属层的堆叠中形成通孔，并且填充有共形扩散阻挡层和第二金属层。一个关键特征是可以选择蚀刻工艺来改变通孔底部的形状和位置。在第一金属层中形成圆形或部分圆形的底部，以减小扩散阻挡层附近的机械应力。另一方面，当第一金属层暴露于后续处理步骤时，选择在TiN ARC上或其中停止的平底，这是首要考虑的问题。发现耐电迁移性低于在第一金属层中形成的平坦底部的通孔结构。

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