专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4192683A Photographic light-sensitive material 失效
标题翻译：摄影感光材料
公开(公告)号：US4192683A
公开(公告)日：1980-03-11
申请号：US843318
申请日：1977-10-18
申请人： Eiichi Sakamoto , Masao Ishihara , Kazuo Nakazato , Hiroshi Yamada , Sadatugu Terada , Kenichi Kitahara , Naoto Abe , Mamoru Komiya , Masaru Kanbe
发明人： Eiichi Sakamoto , Masao Ishihara , Kazuo Nakazato , Hiroshi Yamada , Sadatugu Terada , Kenichi Kitahara , Naoto Abe , Mamoru Komiya , Masaru Kanbe
IPC分类号： G03C1/043 , G03C1/38 , G03C1/89 , G03C1/76 , G03C1/02
CPC分类号： G03C1/38 , G03C1/043 , G03C1/895 , Y10S430/136
摘要： A photographic light-sensitive material comprising a layer which contains a compound represented by the following Formula I ##STR1## wherein R.sub.1 is an alkyl group having 1 to 18 carbon atoms, R.sub.2 is a hydrogen atom or an alkyl group having 1 to 18 carbon atoms with a proviso that when R.sub.2 is a hydrogen atom, R.sub.1 is an alkyl group having 1 to 7 carbon atoms, M is a cation and n is a number of 1 to 50.
摘要翻译：照相感光材料，其包含含有由下式I表示的化合物的层，其中R 1为具有1至18个碳原子的烷基，R 2为氢原子或具有1至18个碳原子的烷基条件是当R 2为氢原子时，R 1为具有1至7个碳原子的烷基，M为阳离子，n为1至50的数。

2. 发明申请

US20060035434A1 Longitudinal misfet manufacturing method, Longitudinal misfet, semiconductor storage device manufacturing method, and semiconductor storage device 有权
标题翻译：纵向错配制造方法，纵向错误，半导体存储装置制造方法以及半导体存储装置
公开(公告)号：US20060035434A1
公开(公告)日：2006-02-16
申请号：US10493443
申请日：2002-10-10
申请人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruaki Kisu , Teruo Kisu , Haruko Kisu , Satoru Haga
发明人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruaki Kisu , Teruo Kisu , Haruko Kisu , Satoru Haga
IPC分类号： H01L21/336
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , Y10S257/903
摘要： A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).
摘要翻译：半导体存储器件包括具有源极区，沟道形成区，漏极区和形成在沟道形成区的侧壁上的栅极的垂直MISFET，栅极绝缘膜。在制造半导体存储器件时，可以通过以下方式实现泄漏电流（截止电流）较小的垂直MISFET：将与扩散到构成的多晶硅膜（10）的磷相反的导电类型的反向掺杂硼来自构成垂直MISFET的源极区域的n型多晶硅膜（7）的沟道形成区域和上述多晶硅膜（10）; 并降低多晶硅膜（10）中的有效杂质浓度。

3. 发明授权

US5227660A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5227660A
公开(公告)日：1993-07-13
申请号：US648309
申请日：1991-01-29
申请人： Masatada Horiuchi , Kazuo Nakazato
发明人： Masatada Horiuchi , Kazuo Nakazato
IPC分类号： H01L27/102 , H01L27/108
CPC分类号： H01L27/10841 , H01L27/1023
摘要： This invention relates to a semiconductor device, in which a singlecrystal semiconductor substrate whose principal surface is a (111) plane is etched from the principal surface thereof in the direction perpendicular thereto to form a vertical trench and a lateral trench is formed at the bottom portion of the side wall of the vertical trench by effecting an anisotropic etching with respect to crystallographical axes so that the etching proceeds in the direction of axis, the lateral and the vertical trenches being filled with polycrystalline or amorphous semiconductor or insulator.
摘要翻译：本发明涉及一种半导体器件，其中主表面为（111）面的单晶半导体衬底从其主表面沿与其垂直的方向蚀刻以形成垂直沟槽，并且横向沟槽形成在底部通过相对于晶体轴进行各向异性蚀刻使垂直沟槽的侧壁沿<110>轴的方向进行，横向和垂直沟槽被多晶或非晶半导体或绝缘体填充。

4. 发明授权

US4956688A Radiation resistant bipolar memory 失效
标题翻译：耐辐射双极记忆
公开(公告)号：US4956688A
公开(公告)日：1990-09-11
申请号：US374570
申请日：1989-06-27
申请人： Noriyuki Honma , Tohru Nakamura , Kazuo Nakazato , Motoaki Matsumoto , Tetsuya Hayashida , Masaharu Kubo , Kazuhiko Sagara
发明人： Noriyuki Honma , Tohru Nakamura , Kazuo Nakazato , Motoaki Matsumoto , Tetsuya Hayashida , Masaharu Kubo , Kazuhiko Sagara
IPC分类号： H01L27/102 , H01L29/732
CPC分类号： H01L27/1025 , H01L29/7327
摘要： A bipolar memory of a construction having high immunity from soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuit of the memory cell, are inverted, and the load device thereof has a shielding arrangement for shielding the flip flop from the noise produced within the substrate. Either pnp type transistors or Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in the region where the device is provided. A reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.
摘要翻译：提供了具有高抗免除由α射线引起的软误差的结构的双极记忆。触发器的晶体管，即存储单元的基本电路被反转，并且其负载装置具有用于屏蔽触发器与基板内产生的噪声的屏蔽装置。采用pnp型晶体管或肖特基势垒二极管作为负载器件。在设置有器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层。跨越掩埋层和掺杂层施加反向偏压，以切断衬底内产生的噪声。

5. 发明授权

US4887145A Semiconductor device in which electrodes are formed in a self-aligned manner 失效
标题翻译：电极以自对准方式形成的半导体器件
公开(公告)号：US4887145A
公开(公告)日：1989-12-12
申请号：US937610
申请日：1986-12-03
申请人： Katsuyoshi Washio , Tohru Nakamura , Kazuo Nakazato , Masatada Horiuchi , Tetsuya Hayashida
发明人： Katsuyoshi Washio , Tohru Nakamura , Kazuo Nakazato , Masatada Horiuchi , Tetsuya Hayashida
IPC分类号： H01L21/285 , H01L21/32 , H01L21/331 , H01L29/423 , H01L29/732 , H01L29/04
CPC分类号： H01L29/66272 , H01L21/28525 , H01L21/32 , H01L29/42304 , H01L29/7325
摘要： A bipolar transistor capable of operating at high speeds. In a bipolar transistor designed for operation at high speeds, a polycrystalline silicon layer used as a base electrode effects is a contact area with respect to the base region which lacks precision or tends to increase. Further, when the transistor is formed in a small size, the ratio of the contact area with respect to the polycrystalline area increases, making it difficult to increase the operation speed. In order to reduce the contact area of the polycrystalline silicon layer, this invention deals with the structure in which the polycrystalline silicon layer is brought into contact with a portion near the edge of the convex semiconductor layer maintaining a small size and a high precision.
摘要翻译：能够高速运行的双极晶体管。在设计用于高速运行的双极晶体管中，用作基极效应的多晶硅层是相对于缺少精度或倾向于增加的基极区域的接触面积。此外，当晶体管形成为小尺寸时，接触面积相对于多晶面积的比率增加，使得难以提高操作速度。为了减少多晶硅层的接触面积，本发明涉及多晶硅层与凸半导体层的边缘附近的部分接触的结构，保持小尺寸和高精度。

6. 发明授权

US4858184A Radiation resistant bipolar memory 失效
标题翻译：耐辐射双极记忆
公开(公告)号：US4858184A
公开(公告)日：1989-08-15
申请号：US42698
申请日：1987-04-27
申请人： Noriyuki Homma , Tohru Nakamura , Kazuo Nakazato , Motoaki Matsumoto , Tetsuya Hayashida , Masaharu Kubo , Kazuhiko Sagara
发明人： Noriyuki Homma , Tohru Nakamura , Kazuo Nakazato , Motoaki Matsumoto , Tetsuya Hayashida , Masaharu Kubo , Kazuhiko Sagara
IPC分类号： G11C11/411
CPC分类号： G11C11/4113 , G11C11/4116
摘要： A bipolar memory of a construction having high immunity to soft error attributable to alpha rays is provided. The transistors of a flip flop, i.e., the essential circuitry of the memory cell, are inverted and the load device thereof has shielding means for shielding the flip flop from the noise produced within the substrate. Bipolar transistors and Schottky barrier diodes are employed as the load devices. A buried layer (ordinarily, an n type layer) and a doped layer of the reverse conductivity type (ordinarily the p type) are formed in a region where the device is provided, and a reverse bias is applied across the buried layer and the doped layer to shut off the noise produced within the substrate.
摘要翻译：提供了具有对由α射线引起的软误差具有高免疫性的结构的双极记忆。触发器的晶体管，即存储器单元的基本电路被反转，并且其负载装置具有屏蔽装置，用于屏蔽触发器与衬底内产生的噪声。采用双极晶体管和肖特基势垒二极管作为负载器件。在设置器件的区域中形成掩埋层（通常为n型层）和反向导电型（通常为p型）的掺杂层，并且跨越掩埋层施加反向偏压，并且掺杂以切断衬底内产生的噪音。

7. 发明授权

US4809828A One-way damping valve mechanism for hydraulic damper 失效
标题翻译：液压阻尼器单向阻尼阀机构
公开(公告)号：US4809828A
公开(公告)日：1989-03-07
申请号：US69037
申请日：1987-07-01
申请人： Kazuo Nakazato
发明人： Kazuo Nakazato
IPC分类号： F16F9/348
CPC分类号： F16F9/348
摘要： A one-way damping valve mechanism in a hydraulic damper having a first hydraulic chamber defined in a cylinder, and a piston rod having an inner end on which there is mounted a piston slidably fitted in the cylinder, divides the first hydraulic chamber into a second hydraulic chamber and a third hydraulic chamber. The valve mechansim produces a damping force when the piston is moved in a prescribed direction to move working oil from the second hydraulic chamber into the third hydraulic chamber. The valve mechanism comprises a subvalve for defining a first hydraulic passage to generate a damping force when the piston moves at an extremely low speed in the prescribed direction, and a main valve for defining a second hydraulic passage to generate a damping force when the piston moves in a medium/high speed range in the prescribed direction.
摘要翻译：一种液压阻尼器中的单向阻尼阀机构，具有限定在气缸中的第一液压室，以及活塞杆，其内端安装有可滑动地装配在气缸中的活塞，将第一液压室分为第二液压室液压室和第三液压室。当活塞沿规定方向移动以将工作油从第二液压室移动到第三液压室中时，阀门机构产生阻尼力。阀机构包括用于限定第一液压通道的子阀，以在活塞以规定方向以极低的速度移动时产生阻尼力;以及主阀，用于限定第二液压通道，以在活塞移动时产生阻尼力在规定方向的中/高速范围内。

8. 发明申请

US20100007326A1 Material Detector 有权
标题翻译：材料检测器
公开(公告)号：US20100007326A1
公开(公告)日：2010-01-14
申请号：US12308769
申请日：2007-07-11
申请人： Kazuo Nakazato
发明人： Kazuo Nakazato
IPC分类号： G01N27/00
CPC分类号： G01N27/4148 , G01N27/4145
摘要： [Object] To realize a small size and high detection accuracy in a substance detection apparatus.[Solving Means] A charge detection field effect transistor and a control circuit therefor are provided in each cell, and the control circuit controls the charge detection field effect transistor so that the drain-source voltage and the drain current of the charge detection field effect transistor are always maintained constant. The control circuit may be formed in a CMOS configuration including a small number of elements in a small area using a standard CMOS integrated circuit technique.
摘要翻译：在物质检测装置中实现小尺寸和高检测精度。解决方案在每个单元中提供电荷检测场效应晶体管及其控制电路，并且控制电路控制电荷检测场效应晶体管，使得电荷检测场效应晶体管的漏 - 源电压和漏电流始终保持不变。控制电路可以使用标准CMOS集成电路技术形成为包括少量元件的CMOS配置。

9. 发明授权

US07132713B2 Controllable conduction device with electrostatic barrier 失效
标题翻译：带静电屏障的可控制传导装置
公开(公告)号：US07132713B2
公开(公告)日：2006-11-07
申请号：US10121596
申请日：2002-04-15
申请人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshikazu Shimada , Hideo Sunami , Tatsuya Teshima , Toshiyuki Mine , Ken Yamaguchi
发明人： Kazuo Nakazato , Kiyoo Itoh , Hiroshi Mizuta , Toshikazu Shimada , Hideo Sunami , Tatsuya Teshima , Toshiyuki Mine , Ken Yamaguchi
IPC分类号： H01L29/76 , H01L31/109
CPC分类号： H01L27/10858 , B82Y10/00 , G11C11/16 , H01L21/28273 , H01L27/10808 , H01L27/1082 , H01L27/10873 , H01L27/10876 , H01L27/11 , H01L29/154 , H01L29/42324 , H01L29/66825 , H01L29/772 , H01L29/78609 , H01L29/78618 , H01L29/78642 , H01L29/78687 , H01L29/7881 , H01L29/882
摘要： A controllable conduction device in the form of a transistor comprises source and drain regions 5, 2 between which extends a conduction path P for charge carriers, a gate 4 for controlling charge carrier flow along the conduction path and a multiple layer structure 3 providing a multiple tunnel junction configuration in the conduction path, with the result that current leakage is blocked by the multiple tunnel junction configuration when the transistor is in its off state. Vertical and lateral transistor configurations are described, together with use of the transistor in complimentary pairs and for a random access memory cell. Improved gate structures are described which are also applicable to memory devices that incorporate the tunnel barrier configuration to store charge on the memory node.
摘要翻译：晶体管形式的可控导电器件包括源极和漏极区域5，其间延伸用于电荷载流子的导电路径P，用于控制沿导电路径的电荷载流子的栅极4和提供多个导通路径中的隧道结结构，结果当晶体管处于其截止状态时，漏电流被多重隧道结构造阻塞。描述了垂直和横向晶体管配置，以及使用晶体管的互补对和随机存取存储器单元。描述了改进的栅极结构，其也适用于结合隧道势垒配置以在存储器节点上存储电荷的存储器件。

10. 发明授权

US06762951B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US06762951B2
公开(公告)日：2004-07-13
申请号：US10330077
申请日：2002-12-30
申请人： Kiyoo Itoh , Kazuo Nakazato
发明人： Kiyoo Itoh , Kazuo Nakazato
IPC分类号： G11C1124
CPC分类号： G11C11/4076 , G11C11/404 , G11C11/405 , G11C16/0408 , G11C2207/2281 , G11C2207/229
摘要： A semiconductor integrated circuit device utilizing a memory cell containing a transistor to write information and a storage MOSFET to retain an information voltage in the gate, a word line placed to intersect with a write data line and a read data line, for connecting to the control terminal of the write transistor and a memory cell array for issuing an output on the read data line corresponding to the read signal from said memory cell in response to a select signal from said write transistor and by means of a data select circuit select one from among said plurality of read data lines from the data line select circuit and connect to either a first or second common data line, precharge said read data line to a first voltage within a first period, discharge said read data line to a second voltage by means of a second storage MOSFET of said memory cell set to on status for said word line selected within the second period, precharge said first and second common data lines to a third voltage between said first and said second voltages within said first period and, amplify the read signal appearing on either of the common data lines from the read data line selected by said data line select circuit within said second period by using the precharge voltage on said other common data line as a reference voltage.
摘要翻译：一种半导体集成电路器件，其利用包含晶体管来写入信息的存储单元和存储MOSFET来保持栅极中的信息电压，放置为与写入数据线和读取数据线相交的字线，用于连接到控制器写入晶体管的端子和用于响应于来自所述写入晶体管的选择信号而从所述存储单元发出对应于读取信号的所述读取数据线上的输出的存储单元阵列，并且借助于数据选择电路，从所述多条读取数据线从数据线选择电路连接到第一或第二公共数据线，在第一周期内将所述读取数据线预充电到第一电压，借助于所述存储器单元的第二存储MOSFET设置为在所述第二周期内选择的所述字线的状态，将所述第一和第二公共数据线预充电到第三伏特在所述第一周期内的所述第一和所述第二电压之间，并且在所述第二周期内通过使用所述另一个上的预充电电压来放大在所述第二周期内由所述数据线选择电路选择的读数据线上出现在任一公共数据线上的读信号公共数据线作为参考电压。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式