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1. 发明授权

US08420527B2 Semiconductor integrated circuit device 失效
公开(公告)号：US08420527B2
公开(公告)日：2013-04-16
申请号：US13196967
申请日：2011-08-03
申请人： Yasushi Koubuchi , Koichi Nagasawa , Masahiro Moniwa , Youhei Yamada , Toshifumi Takeda
发明人： Yasushi Koubuchi , Koichi Nagasawa , Masahiro Moniwa , Youhei Yamada , Toshifumi Takeda
IPC分类号： H01L21/302
CPC分类号： H01L23/562 , G03F9/7076 , G03F9/7084 , H01L21/31053 , H01L21/76819 , H01L21/76838 , H01L23/522 , H01L23/585 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05554 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/05042 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

2. 发明授权

US07972920B2 Semiconductor memory device and a method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device 有权
标题翻译：半导体存储器件及其制造方法，制造垂直MISFET和垂直MISFET的方法以及半导体器件和半导体器件的制造方法
公开(公告)号：US07972920B2
公开(公告)日：2011-07-05
申请号：US12700344
申请日：2010-02-04
申请人： Hiraku Chakihara , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
发明人： Hiraku Chakihara , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
IPC分类号： H01L21/8244 , G11C11/40
CPC分类号： H01L29/6675 , H01L21/823885 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/7833 , H01L29/78642
摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
摘要翻译：垂直MISFET形成在驱动MISFET和传输MISFET上。垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极插入其间。在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。下半导体层，中间半导体层和上半导体层均由硅膜构成。下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

3. 发明申请

US20110101297A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110101297A1
公开(公告)日：2011-05-05
申请号：US12987606
申请日：2011-01-10
申请人： Masahiro MONIWA , Nozomu Matsuzaki , Riichiro Takemura
发明人： Masahiro MONIWA , Nozomu Matsuzaki , Riichiro Takemura
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.
摘要翻译：实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞和堆叠在其上的插头。多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。

4. 发明授权

US07714314B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07714314B2
公开(公告)日：2010-05-11
申请号：US11775474
申请日：2007-07-10
申请人： Masahiro Moniwa , Nozomu Matsuzaki , Riichiro Takemura
发明人： Masahiro Moniwa , Nozomu Matsuzaki , Riichiro Takemura
IPC分类号： H01L29/02 , H01L31/032
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.
摘要翻译：实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞和堆叠在其上的插头。多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。

5. 发明授权

US07474003B2 Semiconductor integrated circuit device 有权
公开(公告)号：US07474003B2
公开(公告)日：2009-01-06
申请号：US11802450
申请日：2007-05-23
申请人： Yasushi Koubuchi , Koichi Nagasawa , Masahiro Moniwa , Youhei Yamada , Toshifumi Takeda
发明人： Yasushi Koubuchi , Koichi Nagasawa , Masahiro Moniwa , Youhei Yamada , Toshifumi Takeda
IPC分类号： H01L29/76
CPC分类号： H01L23/562 , G03F9/7076 , G03F9/7084 , H01L21/31053 , H01L21/76819 , H01L21/76838 , H01L23/522 , H01L23/585 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05554 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/05042 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

6. 发明申请

US20080011997A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080011997A1
公开(公告)日：2008-01-17
申请号：US11775474
申请日：2007-07-10
申请人： Masahiro MONIWA , Nozomu Matsuzaki , Riichiro Takemura
发明人： Masahiro MONIWA , Nozomu Matsuzaki , Riichiro Takemura
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C11/5678 , G11C13/0004 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/1675
摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration at the time of using a phase change film as a memory element.Between MISFET of the region which forms one memory cell, and MISFET which adjoined it, each source of MISFET adjoins in the front surface of a semiconductor substrate, insulating. And the multi-layer structure of a phase change film, and the electric conduction film of specific resistance lower than the specific resistance is formed in the plan view of the front surface of a semiconductor substrate ranging over each source of both MISFET, and a plug and a plug stacked on it. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of a semiconductor substrate, and an electric conduction film sends the current of a parallel direction on the surface of a semiconductor substrate.
摘要翻译：实现了容易形成相变膜的半导体器件及其制造方法，在使用相变膜作为存储元件时实现高集成度。在形成一个存储单元的区域的MISFET和与其相邻的MISFET之间，MISFET的每个源极邻接在半导体衬底的前表面中，绝缘。并且在两个MISFET的每个源上的半导体衬底的前表面的平面图中形成相变膜的多层结构和比电阻率低的电阻率的导电膜，并且插塞和堆叠在其上的插头。多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上发送平行方向的电流。

7. 发明授权

US07163870B2 Semiconductor integrated circuit device 有权
标题翻译：半导体集成电路器件
公开(公告)号：US07163870B2
公开(公告)日：2007-01-16
申请号：US10951939
申请日：2004-09-29
申请人： Yasushi Koubuchi , Koichi Nagasawa , Masahiro Moniwa , Youhei Yamada , Toshifumi Takeda
发明人： Yasushi Koubuchi , Koichi Nagasawa , Masahiro Moniwa , Youhei Yamada , Toshifumi Takeda
IPC分类号： H01L21/76
CPC分类号： H01L23/562 , G03F9/7076 , G03F9/7084 , H01L21/31053 , H01L21/76819 , H01L21/76838 , H01L23/522 , H01L23/585 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05554 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/05042 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.
摘要翻译：在覆盖形成在半导体衬底的主表面上的MISFETQ1的层间绝缘膜上形成互连，而虚设互连设置在与这种相互连接的区域中。虚拟互连也布置在划线区域中。在接合焊盘和标记的周边不形成虚拟互连。此外，设置MISFET的栅电极和由相同层形成的虚拟栅极互连。此外，虚设区域设置在浅沟槽元件隔离区域中。在这样的虚设部件设置之后，通过CMP方法将绝缘膜平坦化。

8. 发明授权

US07161215B2 Semiconductor memory device and method of manufacturing the same, a method of manufacturing a vertical MISFET and a vertical MISFET, and a method of manufacturing a semiconductor device and a semiconductor device 有权
标题翻译：半导体存储器件及其制造方法，制造垂直MISFET和垂直MISFET的方法以及半导体器件和半导体器件的制造方法
公开(公告)号：US07161215B2
公开(公告)日：2007-01-09
申请号：US11418029
申请日：2006-05-05
申请人： Hiraku Chakihara , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
发明人： Hiraku Chakihara , Kousuke Okuyama , Masahiro Moniwa , Makoto Mizuno , Keiji Okamoto , Mitsuhiro Noguchi , Tadanori Yoshida , Yasuhiko Takahshi , Akio Nishida
IPC分类号： H01L29/78 , G11C11/412
CPC分类号： H01L29/6675 , H01L21/823885 , H01L27/105 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/7833 , H01L29/78642
摘要： Vertical MISFETs are formed over drive MISFETs and transfer MISFETs. The vertical MISFETs comprise rectangular pillar laminated bodies each formed by laminating a lower semiconductor layer (drain), an intermediate semiconductor layer, and an upper semiconductor layer (source), and gate electrodes formed on corresponding side walls of the laminated bodies with gate insulating films interposed therebetween. In each vertical MISFET, the lower semiconductor layer constitutes a drain, the intermediate semiconductor layer constitutes a substrate (channel region), and the upper semiconductor layer constitutes a source. The lower semiconductor layer, the intermediate semiconductor layer and the upper semiconductor layer are each comprised of a silicon film. The lower semiconductor layer and the upper semiconductor layer are doped with a p type and constituted of a p type silicon film.
摘要翻译：垂直MISFET形成在驱动MISFET和传输MISFET上。垂直MISFET包括通过层叠下半导体层（漏极），中间半导体层和上半导体层（源极）形成的矩形柱层叠体以及在层叠体的相应侧壁上形成有栅极绝缘膜的栅电极插入其间。在每个垂直MISFET中，下半导体层构成漏极，中间半导体层构成衬底（沟道区），上半导体层构成源极。下半导体层，中间半导体层和上半导体层均由硅膜构成。下半导体层和上半导体层掺杂有p型并由p型硅膜构成。

9. 发明申请

US20050253143A1 Semiconductor memory device using vertical-channel transistors 失效
标题翻译：半导体存储器件采用垂直沟道晶体管
公开(公告)号：US20050253143A1
公开(公告)日：2005-11-17
申请号：US11168872
申请日：2005-06-29
申请人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
发明人： Norikatsu Takaura , Hideyuki Matsuoka , Riichiro Takemura , Kousuke Okuyama , Masahiro Moniwa , Akio Nishida , Kota Funayama , Tomonori Sekiguchi
IPC分类号： G11C11/41 , H01L21/8234 , H01L21/8244 , H01L27/00 , H01L27/06 , H01L27/088 , H01L27/10 , H01L27/11 , H01L29/10
CPC分类号： H01L27/11 , H01L27/0688 , H01L27/1104
摘要： The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.
摘要翻译：本发明提供一种包括多个字线，多个位线以及多个静态存储单元的半导体存储器件，每个静态存储器单元具有第一，第二，第三，第四，第五和第六和第六晶体管。尽管第一，第二，第三和第四晶体管的每个通道与半导体存储器件的衬底垂直地形成。形成第五晶体管和第六晶体管的源极或漏极的半导体区域形成与衬底相反的PN结。根据本发明的另一方面，本发明的SRAM器件具有多个SRAM单元，其中至少一个是在衬底上包括至少四个垂直晶体管的垂直SRAM单元，并且每个垂直晶体管包括源极，排水管和其间的通道在以大于零度的角度穿入衬底表面的一个对准线对中。

10. 发明申请

US20050040538A1 Semiconductor integrated circuit device 有权
公开(公告)号：US20050040538A1
公开(公告)日：2005-02-24
申请号：US10956159
申请日：2004-10-04
申请人： Yasushi Koubuchi , Koichi Nagasawa , Masahiro Moniwa , Youhei Yamada , Toshifumi Takeda
发明人： Yasushi Koubuchi , Koichi Nagasawa , Masahiro Moniwa , Youhei Yamada , Toshifumi Takeda
IPC分类号： H01L21/76 , H01L21/304 , H01L21/3205 , H01L21/768 , H01L21/8242 , H01L23/00 , H01L27/108 , H01L21/336
CPC分类号： H01L23/562 , G03F9/7076 , G03F9/7084 , H01L21/31053 , H01L21/76819 , H01L21/76838 , H01L23/522 , H01L23/585 , H01L24/05 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/05554 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01058 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/05042 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/14 , H01L2924/19041 , H01L2924/30105 , H01L2924/00
摘要： Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.

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