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1. 发明申请

US20070202638A1 Vertical misfet manufacturing method, vertical misfet, semiconductor memory device manufacturing method, and semiconductor memory device 审中-公开
标题翻译：垂直错位制造方法，垂直错位，半导体存储器件制造方法和半导体存储器件
公开(公告)号：US20070202638A1
公开(公告)日：2007-08-30
申请号：US11790130
申请日：2007-04-24
申请人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruaki Kisu , Teruo Kisu , Haruko Kisu , Satoru Haga
发明人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruaki Kisu , Teruo Kisu , Haruko Kisu , Satoru Haga
IPC分类号： H01L21/84
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , Y10S257/903
摘要： A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).
摘要翻译：半导体存储器件包括具有源极区，沟道形成区，漏极区和形成在沟道形成区的侧壁上的栅极的垂直MISFET，栅极绝缘膜。在制造半导体存储器件时，可以通过以下方式实现泄漏电流（截止电流）较小的垂直MISFET：将与扩散到构成的多晶硅膜（10）的磷相反的导电类型的反向掺杂硼来自构成垂直MISFET的源极区域的n型多晶硅膜（7）的沟道形成区域和上述多晶硅膜（10）; 并降低多晶硅膜（10）中的有效杂质浓度。

2. 发明申请

US20060035434A1 Longitudinal misfet manufacturing method, Longitudinal misfet, semiconductor storage device manufacturing method, and semiconductor storage device 有权
标题翻译：纵向错配制造方法，纵向错误，半导体存储装置制造方法以及半导体存储装置
公开(公告)号：US20060035434A1
公开(公告)日：2006-02-16
申请号：US10493443
申请日：2002-10-10
申请人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruaki Kisu , Teruo Kisu , Haruko Kisu , Satoru Haga
发明人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruaki Kisu , Teruo Kisu , Haruko Kisu , Satoru Haga
IPC分类号： H01L21/336
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , Y10S257/903
摘要： A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).
摘要翻译：半导体存储器件包括具有源极区，沟道形成区，漏极区和形成在沟道形成区的侧壁上的栅极的垂直MISFET，栅极绝缘膜。在制造半导体存储器件时，可以通过以下方式实现泄漏电流（截止电流）较小的垂直MISFET：将与扩散到构成的多晶硅膜（10）的磷相反的导电类型的反向掺杂硼来自构成垂直MISFET的源极区域的n型多晶硅膜（7）的沟道形成区域和上述多晶硅膜（10）; 并降低多晶硅膜（10）中的有效杂质浓度。

3. 发明授权

US06861692B2 Method of manufacturing semiconductor device and semiconductor device 失效
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US06861692B2
公开(公告)日：2005-03-01
申请号：US10338002
申请日：2003-01-08
申请人： Hiroshi Kujirai , Masahiro Moniwa , Kazuo Nakazato , Teruo Kisu , Haruko Kisu , Hideyuki Matsuoka , Tsuyoshi Tabata
发明人： Teruaki Kisu
IPC分类号： H01L21/768 , H01L21/334 , H01L21/8242 , H01L27/108 , H01L29/76 , H01L29/78 , H01L29/786
CPC分类号： H01L27/10864 , H01L27/10832 , H01L27/1087 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.
摘要翻译：在半导体衬底的存储单元形成区域中设置的沟槽型电容器的正上方设置有垂直MIS，在半导体衬底的外围电路形成区域设置横向nMIS。在形成电容器之后，形成横向nMIS。此外，在形成横向nMIS之后，形成垂直MIS。此外，在形成电容器之后，形成外围电路的隔离部分。

4. 发明授权

US06787411B2 Method of manufacturing semiconductor memory device and semiconductor memory device 失效
标题翻译：制造半导体存储器件和半导体存储器件的方法
公开(公告)号：US06787411B2
公开(公告)日：2004-09-07
申请号：US10330448
申请日：2002-12-30
申请人： Teruaki Kisu , Kazuo Nakazato , Masahito Takahashi
发明人： Teruaki Kisu , Kazuo Nakazato , Masahito Takahashi
IPC分类号： H01L218244
CPC分类号： H01L27/108 , H01L27/0688 , H01L27/105 , H01L27/1052
摘要： Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.
摘要翻译：公开了能够使存储单元尺寸小型化的增益单元结构及其制造方法。存储单元由读取MIS晶体管和写入MIS晶体管构成。读取MIS晶体管具有形成在半导体衬底的主表面上的一对n +型半导体区域（源极区域和漏极区域）和形成在n +型半导体区域13的路径上的第一栅极电极经由第一栅绝缘膜。写入MIS晶体管布置在读取MIS晶体管上，并且具有通过以此顺序层叠下半导体层（源极区），中间半导体层（沟道形成区）和上半导体层（漏极区）而形成的层叠结构。写入MIS晶体管具有垂直结构，其中第二栅极经由第二栅极绝缘膜布置在层状结构的两个侧壁上。

5. 发明授权

US06501116B2 Semiconductor memory device with MIS transistors 失效
标题翻译：具有MIS晶体管的半导体存储器件
公开(公告)号：US06501116B2
公开(公告)日：2002-12-31
申请号：US10026769
申请日：2001-12-27
申请人： Teruaki Kisu , Kazuo Nakazato , Masahito Takahashi
发明人： Teruaki Kisu , Kazuo Nakazato , Masahito Takahashi
IPC分类号： H01L2708
CPC分类号： H01L27/108 , H01L27/0688 , H01L27/105 , H01L27/1052
摘要： Disclosed are a gain cell structure capable of making a memory cell compact in size and a method of manufacturing the same at low cost. A memory cell is constituted of a reading MIS transistor and a writing MIS transistor. The reading MIS transistor has a pair of n+ type semiconductor regions (source region and drain region) formed on a main surface of a semiconductor substrate and a first gate electrode formed on a path of the n+ type semiconductor regions 13 via a first gate insulating film. The writing MIS transistor is arranged on the reading MIS transistor and has a layered structure made by laminating a lower semiconductor layer (source region), an intermediate semiconductor layer (channel forming region), and an upper semiconductor layer (drain region) in this order. The writing MIS transistor has a vertical structure in which a second gate electrode is arranged on both sidewalls of the layered structure via a second gate insulating film.
摘要翻译：公开了能够使存储单元尺寸小型化的增益单元结构及其制造方法。存储单元由读取MIS晶体管和写入MIS晶体管构成。读取MIS晶体管具有形成在半导体衬底的主表面上的一对n +型半导体区域（源极区域和漏极区域）以及经由第一栅极绝缘膜形成在n +型半导体区域13的路径上的第一栅极电极。写入MIS晶体管布置在读取MIS晶体管上，并且具有通过以此顺序层叠下半导体层（源极区），中间半导体层（沟道形成区）和上半导体层（漏极区）而形成的层叠结构。写入MIS晶体管具有垂直结构，其中第二栅极经由第二栅极绝缘膜布置在层状结构的两个侧壁上。

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