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1. 发明授权

US06442837B1 Method of manufacturing a valve element 失效
标题翻译：制造阀元件的方法
公开(公告)号：US06442837B1
公开(公告)日：2002-09-03
申请号：US09753634
申请日：2001-01-03
申请人： Satoru Haga , Shunji Kurono
发明人： Satoru Haga , Shunji Kurono
IPC分类号： B23P1500
CPC分类号： F16K1/36 , F16K31/06 , Y10T29/49405 , Y10T29/49412
摘要： A method of manufacturing a valve element for a solenoid valve to open and close a valve seat, comprising the steps of; preparing a leaf spring including an outer peripheral ring section and a hub section having a central hole, forming a ring-shaped outer peripheral seal along the peripheral ring section, and preparing a movable core having a cup-shaped cross section and including a cylindrical section and an end wall section. The method further comprising, forming a valve seal on the end wall section by placing the movable core and the leaf spring in a mold and aligning and holding the leaf spring and the stepped section in contact with each other, and aligning a holder ring along an outer periphery of the movable core, and bringing the holder ring into engagement with the movable core, wherein the leaf spring and the movable core are rigidly secured to each other.
摘要翻译：一种制造电磁阀的阀元件以打开和关闭阀座的方法，包括以下步骤：制备包括外周环部分的片簧和具有中心孔的轮毂部分，沿周缘环形成环形外周密封件，并制备具有杯状横截面并包括圆柱形部分的可动芯体和端壁部分。该方法还包括：通过将可动铁芯和板簧放置在模具中并将片簧和台阶部分对准并保持彼此接触，并将夹持环沿着可动芯的外周，并且使保持环与可动铁芯接合，其中板簧和可动铁心彼此刚性地固定。

2. 发明授权

US06290205B1 Valve element and method of manufacturing the same 失效
标题翻译：阀元件及其制造方法
公开(公告)号：US06290205B1
公开(公告)日：2001-09-18
申请号：US09455689
申请日：1999-12-07
申请人： Satoru Haga , Shunji Kurono
发明人： Satoru Haga , Shunji Kurono
IPC分类号： F16K3102
CPC分类号： F16K1/36 , F16K31/06 , Y10T29/49405 , Y10T29/49412
摘要： A valve element with a disk-shaped leaf spring carrying a movable core in a solenoid valve to open/close a valve seat. The leaf spring includes an outer peripheral ring section, a hub section having a central hole and a plurality of radially arranged arm sections connected between the ring; section and hub section. A seal of elastic material extends along the outer peripheral, ring section of the leaf spring. The movable core has a cylindrical section and an end wall section having a through central hole. The cylindrical section has a stepped section on its outer periphery adapted to be held in contact with the leaf spring. A valve seal is formed on the end wall section through vulcanization and molding, and has a main body section on the outer surface of the end wall section, a small diameter section in said through hole and a holder section connected to the main body section by the small diameter section and inner surface of the end wall section. The movable core and leaf spring are rigidly secured to each other by a thermal plastic ring engaged in a groove on the outer periphery of the movable core.
摘要翻译：一种具有盘形片簧的阀元件，其在电磁阀中承载可动铁芯以打开/关闭阀座。板簧包括外周环部分，具有中心孔的毂部分和连接在环之间的多个径向布置的臂部分; 部分和集线器部分。弹性材料的密封沿着板簧的外周，环形部分延伸。可动芯具有圆筒形部分和具有贯穿中心孔的端壁部分。圆柱形部分在其外周上具有阶梯部分，其适于与片簧保持接触。通过硫化成型在端壁部分上形成阀密封件，并且在端壁部分的外表面上具有主体部分，在所述通孔中具有小直径部分，以及通过以下方式连接到主体部分的保持部分：小直径部分和端壁部分的内表面。可动铁芯和板簧通过与可移动铁芯的外周上的凹槽啮合的热塑性环而牢固地固定在一起。

3. 发明授权

US5780328A Process for producing semiconductor integrated circuit 失效
标题翻译：半导体集成电路制造工艺
公开(公告)号：US5780328A
公开(公告)日：1998-07-14
申请号：US835197
申请日：1997-04-07
申请人： Kazushi Fukuda , Yasuko Yoshida , Yutaka Hoshino , Naotaka Hashimoto , Kyoichiro Asayama , Yuuki Koide , Keiichi Yoshizumi , Eri Okamoto , Satoru Haga , Shuji Ikeda
发明人： Kazushi Fukuda , Yasuko Yoshida , Yutaka Hoshino , Naotaka Hashimoto , Kyoichiro Asayama , Yuuki Koide , Keiichi Yoshizumi , Eri Okamoto , Satoru Haga , Shuji Ikeda
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238 , H01L21/8239 , H01L21/8244 , H01L27/11 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823871 , H01L27/1052 , H01L27/11 , H01L27/1104
摘要： When the source and drain regions (an n.sup.- type semiconductor region and an n.sup.+ type semiconductor region) of a complementary MISFET and a p-type semiconductor region for use as a punch-through stopper are formed in a p-type well in a substrate having a p- and an n-type well, p-type impurities for the punch-through stopper are suppressed from being supplied to the feeding portion (an n.sup.+ type semiconductor region) of the n-type well.
摘要翻译：当在衬底中的p型阱中形成用作穿通阻挡层的互补MISFET和p型半导体区域的源区和漏区（n型半导体区和n +型半导体区）具有p型和n型阱时，抑制了穿通止动件的p型杂质被供给到n型阱的馈电部（n +型半导体区）。

4. 发明申请

US20070202638A1 Vertical misfet manufacturing method, vertical misfet, semiconductor memory device manufacturing method, and semiconductor memory device 审中-公开
标题翻译：垂直错位制造方法，垂直错位，半导体存储器件制造方法和半导体存储器件
公开(公告)号：US20070202638A1
公开(公告)日：2007-08-30
申请号：US11790130
申请日：2007-04-24
申请人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruaki Kisu , Teruo Kisu , Haruko Kisu , Satoru Haga
发明人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruaki Kisu , Teruo Kisu , Haruko Kisu , Satoru Haga
IPC分类号： H01L21/84
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , Y10S257/903
摘要： A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).
摘要翻译：半导体存储器件包括具有源极区，沟道形成区，漏极区和形成在沟道形成区的侧壁上的栅极的垂直MISFET，栅极绝缘膜。在制造半导体存储器件时，可以通过以下方式实现泄漏电流（截止电流）较小的垂直MISFET：将与扩散到构成的多晶硅膜（10）的磷相反的导电类型的反向掺杂硼来自构成垂直MISFET的源极区域的n型多晶硅膜（7）的沟道形成区域和上述多晶硅膜（10）; 并降低多晶硅膜（10）中的有效杂质浓度。

5. 发明授权

US07244977B2 Longitudinal MISFET manufacturing method, longitudinal MISFET, semiconductor storage device manufacturing method, and semiconductor storage device 有权
标题翻译：纵向MISFET制造方法，纵向MISFET，半导体存储装置制造方法和半导体存储装置
公开(公告)号：US07244977B2
公开(公告)日：2007-07-17
申请号：US10493443
申请日：2002-10-10
申请人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruo Kisu, legal representative , Haruko Kisu, legal representative , Satoru Haga
发明人： Teruaki Kisu, deceased
IPC分类号： H01L29/768
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , Y10S257/903
摘要： A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).
摘要翻译：半导体存储器件包括具有源极区，沟道形成区，漏极区和形成在沟道形成区的侧壁上的栅极的垂直MISFET，栅极绝缘膜。在制造半导体存储器件时，可以通过以下方式实现泄漏电流（截止电流）较小的垂直MISFET：将与扩散到构成的多晶硅膜（10）的磷相反的导电类型的反向掺杂硼来自构成垂直MISFET的源极区域的n型多晶硅膜（7）的沟道形成区域和上述多晶硅膜（10）; 并降低多晶硅膜（10）中的有效杂质浓度。

6. 发明申请

US20060035434A1 Longitudinal misfet manufacturing method, Longitudinal misfet, semiconductor storage device manufacturing method, and semiconductor storage device 有权
标题翻译：纵向错配制造方法，纵向错误，半导体存储装置制造方法以及半导体存储装置
公开(公告)号：US20060035434A1
公开(公告)日：2006-02-16
申请号：US10493443
申请日：2002-10-10
申请人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruaki Kisu , Teruo Kisu , Haruko Kisu , Satoru Haga
发明人： Tsuyoshi Tabata , Kazuo Nakazato , Hiroshi Kujirai , Masahiro Moniwa , Hideyuki Matsuoka , Teruaki Kisu , Teruo Kisu , Haruko Kisu , Satoru Haga
IPC分类号： H01L21/336
CPC分类号： H01L27/10864 , H01L27/10867 , H01L27/10876 , Y10S257/903
摘要： A semiconductor memory device includes a vertical MISFET having a source region, a channel forming region, a drain region, and a gate electrode formed on a sidewall of the channel forming region via a gate insulating film. In manufacturing the semiconductor memory device, the vertical MISFET in which leakage current (off current) is less can be realized by: counter-doping boron of a conductivity type opposite to that of phosphorus diffused into a poly-crystalline silicon film (10) constituting the channel forming region from an n type poly-crystalline silicon film (7) constituting the source region of the vertical MISFET, and the above-mentioned poly-crystalline silicon film (10); and reducing an effective impurity concentration in the poly-crystalline silicon film (10).
摘要翻译：半导体存储器件包括具有源极区，沟道形成区，漏极区和形成在沟道形成区的侧壁上的栅极的垂直MISFET，栅极绝缘膜。在制造半导体存储器件时，可以通过以下方式实现泄漏电流（截止电流）较小的垂直MISFET：将与扩散到构成的多晶硅膜（10）的磷相反的导电类型的反向掺杂硼来自构成垂直MISFET的源极区域的n型多晶硅膜（7）的沟道形成区域和上述多晶硅膜（10）; 并降低多晶硅膜（10）中的有效杂质浓度。

7. 发明授权

US06987043B2 Method of manufacturing semiconductor device having a plurality of trench-type data storage capacitors 失效
标题翻译：具有多个沟槽型数据存储电容器的半导体器件的制造方法
公开(公告)号：US06987043B2
公开(公告)日：2006-01-17
申请号：US10278918
申请日：2002-10-24
申请人： Hiroshi Kujirai , Masahiro Moniwa , Kazuo Nakazato , Teruo Kisu, legal representative , Haruko Kisu, legal representative , Hideyuki Matsuoka , Tsuyoshi Tabata , Satoru Haga
发明人： Teruaki Kisu, deceased
IPC分类号： H01L21/8242
CPC分类号： H01L27/10864 , H01L27/10832 , H01L27/1087 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： A vertical MIS is provided immediately above a trench-type capacitor provided in a memory cell forming region of a semiconductor substrate, and a lateral nMIS is provided in the peripheral circuit forming region of the semiconductor substrate. After forming the capacitor, the lateral nMIS is formed. In addition, after forming the lateral nMIS, the vertical MIS is formed. Furthermore, after forming a capacitor, an isolation part of the peripheral circuit is formed.
摘要翻译：在半导体衬底的存储单元形成区域中设置的沟槽型电容器的正上方设置有垂直MIS，在半导体衬底的外围电路形成区域设置横向nMIS。在形成电容器之后，形成横向nMIS。此外，在形成横向nMIS之后，形成垂直MIS。此外，在形成电容器之后，形成外围电路的隔离部分。

8. 发明授权

US5610856A Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US5610856A
公开(公告)日：1997-03-11
申请号：US610185
申请日：1996-03-04
申请人： Keiichi Yoshizumi , Satoru Haga , Shuji Ikeda , Kiichi Makuta , Takeshi Fukazawa
发明人： Keiichi Yoshizumi , Satoru Haga , Shuji Ikeda , Kiichi Makuta , Takeshi Fukazawa
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8244 , H01L27/11 , G11C11/40
CPC分类号： H01L27/1112 , Y10S257/904
摘要： An increase in the GND resistance and a drop in the resistance against electromigration are minimized when the ground voltage lines for shunting are finely constituted by using an Al wiring of the same layer as the pad layer, owing to the employment of a layout in which the arrangement of connection holes 24, 26 in a pad layer connected to one (data line) of the complementary data lines and the arrangement of connection holes in a pad layer connected to the other one (data line bar) of the complementary data lines, are inverted from each other every two bits of memory cells in the SRAM along the direction in which the complementary data lines extend.
摘要翻译：当使用与衬垫层相同层的Al布线精细地构成用于分流的接地电压线时，由于采用这样的布局，使得电阻增加和电迁移阻抗的降低最小化：在连接到互补数据线的一个（数据线）的衬垫层中的连接孔24,26的布置以及连接到互补数据线的另一个（数据线条）的焊盘层中的连接孔的布置是：沿着互补数据线延伸的方向在SRAM中的每两位存储器单元互相反相。

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