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1. 发明授权

US06868490B1 Methods and apparatus for providing context switching between software tasks with reconfigurable control 失效
标题翻译：用于通过可重新配置的控制在软件任务之间提供上下文切换的方法和装置
公开(公告)号：US06868490B1
公开(公告)日：2005-03-15
申请号：US09598558
申请日：2000-06-21
申请人： Edwin F. Barry , Gerald G. Pechanek , David Carl Strube
发明人： Edwin F. Barry , Gerald G. Pechanek , David Carl Strube
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F9/46 , G06F15/80
CPC分类号： G06F9/30181 , G06F9/30043 , G06F9/30076 , G06F9/30123 , G06F9/3013 , G06F9/30138 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F9/462 , G06F15/8007
摘要： The ManArray core indirect VLIW processor consists of an array controller sequence processor (SP) merged with a processing element (PE0) closely coupling the SP with the PE array and providing the capability to share execution units between the SP and PE0. Consequently, in the merged SP/PE0 a single set of execution units are coupled with two independent register files. To make efficient use of the SP and PE resources, the ManArray architecture specifies a bit in the instruction format, the S/P-bit, to differentiate SP instructions from PE instructions. Multiple register contexts are obtained in the ManArray processor by controlling how the array S/P-bit in the ManArray instruction format is used in conjunction with a context switch bit (CSB) for the context selection of the PE register file or the SP register file. In arrays consisting of more than a single PE, the software controllable context switch mechanism is used to reconfigure the array to take advantage of the multiple context support the merged SP/PE provides. For example, a 1×1 can be configured as a 1×1 with context-0 and as a 1×0 with context-1, a 1×2 can be configured as a 1×2 with context-0 and as a 1×1 with context-1, and a 1×5 can be configured as a 1×5 with context-0 and as a 2×2 with context-1. Other array configurations are clearly possible using the present techniques. In the 1×5/2×2 case, the two contexts could be a 1×5 array (context-0) and a 2×2 array (context-1).
摘要翻译： ManArray核心间接VLIW处理器由阵列控制器序列处理器（SP）组成，与处理元件（PE0）合并，该处理元件（PE0）将SP与PE阵列紧密耦合，并提供在SP和PE0之间共享执行单元的能力。因此，在合并的SP / PE0中，单个执行单元集合与两个独立的寄存器文件耦合。为了有效利用SP和PE资源，ManArray架构指定了指令格式（S / P位）中的一位，以区分SP指令和PE指令。通过控制ManArray指令格式中的阵列S / P位如何与用于PE寄存器文件或SP寄存器文件的上下文选择的上下文切换位（CSB）结合使用，在ManArray处理器中获得多个寄存器上下文。在由多个单独的PE组成的阵列中，软件可控上下文切换机制用于重新配置阵列，以利用合并的SP / PE提供的多个上下文支持。例如，1x1可以被配置为具有上下文0的1x1和具有上下文-1的1x0，1x2可以被配置为具有上下文-1的1x2和具有上下文-1的1x1，并且1x5可以被配置为具有上下文-1的1x2 配置为具有上下文0的1x5和具有上下文-1的2x2。使用本技术可以清楚地看出其它阵列配置。在1x5 / 2x2情况下，两个上下文可能是1x5阵列（上下文0）和2x2阵列（上下文-1）。

2. 发明授权

US06760831B2 Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution 有权
标题翻译：在具有子字执行的基于VLIW的阵列处理器中支持条件执行的方法和装置
公开(公告)号：US06760831B2
公开(公告)日：2004-07-06
申请号：US10114652
申请日：2002-04-01
申请人： Thomas L. Drabenstott , Gerald G. Pechanek , Edwin F. Barry , Charles W. Kurak, Jr.
发明人： Thomas L. Drabenstott , Gerald G. Pechanek , Edwin F. Barry , Charles W. Kurak, Jr.
IPC分类号： G06F1580
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3885 , G06F9/3887 , G06F9/3891 , G06F15/8007
摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.
摘要翻译：使用分层一位，二位或三位编码来定义和编码通用标志（ACF）。每个添加的位提供了先前功能的超集。通过条件组合，可以避免基于复杂条件的顺序一系列条件分支，然后可以将复杂条件用于条件执行。 ACF生成和使用可以由程序员指定。通过改变受影响的标志的数量，条件操作并行性可以被广泛地变化，例如，从VLIW执行中的单处理到八进制处理，以及处理元件（PE）的阵列。多个PE可以同时生成条件信息，程序员能够基于使用处理元件之间的通信接口在不同的处理器中生成的条件来指定一个处理器中的条件执行以传送条件。多处理器阵列中的每个处理器可以独立地具有基于它们的ACF有条件地操作的不同单元。

3. 发明授权

US06216223B1 Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor 有权
标题翻译：用于动态重新配置间接非常长的指令字可缩放处理器的指令流水线的方法和装置
公开(公告)号：US06216223B1
公开(公告)日：2001-04-10
申请号：US09228374
申请日：1999-01-12
申请人： Juan Guillermo Revilla , Edwin F. Barry , Patrick Rene Marchand , Gerald G. Pechanek
发明人： Juan Guillermo Revilla , Edwin F. Barry , Patrick Rene Marchand , Gerald G. Pechanek
IPC分类号： G06F922
CPC分类号： G06F9/3873 , G06F9/30058 , G06F9/30076 , G06F9/30079 , G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/3842 , G06F9/3853 , G06F9/3859 , G06F9/3867 , G06F9/3885
摘要： A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages. In addition, the dynamic reconfigurable pipeline is scalable allowing each processing element (PE) in an array of PEs to expand and compress the pipeline in synchronism allowing iVLIW operations to execute independently in each PE. This is accomplished by having distributed pipelines in operation in parallel, one in each PE and in the controller sequence processor (SP).
摘要翻译： ManArray处理器管线设计通过为需要获取VLIW的SIW提供动态可重配置的指令流水线来解决间接VLIW存储器访问问题，而不会增加分支延迟。通过仅在需要VLIW提取时引入额外的循环，本发明解决了VLIW存储器访问问题。通常，管线保持在扩展状态，直到检测到分支类型或负载VLIW存储器类型操作，将流水线返回到压缩管道操作。当检测到分支类型操作时通过压缩流水线，避免了用于分支操作的附加周期的需要。因此，与具有扩展数量的流水线级的固定管道相比，较短的压缩流水线为分支密集型控制代码提供了更高效的性能。此外，动态可重配置流水线是可扩展的，允许PE阵列中的每个处理元件（PE）同步地扩展和压缩流水线，从而允许iVLIW操作在每个PE中独立执行。这是通过并行运行分布式管道，每个PE中的一个和控制器序列处理器（SP）中实现的。

4. 发明授权

US06954842B2 Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution 失效
标题翻译：在具有子字执行的基于VLIW的阵列处理器中支持条件执行的方法和装置
公开(公告)号：US06954842B2
公开(公告)日：2005-10-11
申请号：US10650301
申请日：2003-08-28
申请人： Thomas L. Drabenstott , Gerald G. Pechanek , Edwin F. Barry , Charles W. Kurak, Jr.
发明人： Thomas L. Drabenstott , Gerald G. Pechanek , Edwin F. Barry , Charles W. Kurak, Jr.
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F9/38 , G06F15/16 , G06F15/80 , G06F15/82 , G06F9/302
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3885 , G06F9/3887 , G06F9/3891 , G06F15/8007
摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.
摘要翻译：使用分层一位，二位或三位编码来定义和编码通用标志（ACF）。每个添加的位提供了先前功能的超集。通过条件组合，可以避免基于复杂条件的顺序一系列条件分支，然后可以将复杂条件用于条件执行。 ACF生成和使用可以由程序员指定。通过改变受影响的标志的数量，条件操作并行性可以被广泛地变化，例如，从VLIW执行中的单处理到八进制处理，以及处理元件（PE）的阵列。多个PE可以同时生成条件信息，程序员能够基于使用处理元件之间的通信接口在不同的处理器中生成的条件来指定一个处理器中的条件执行以传送条件。多处理器阵列中的每个处理器可以独立地具有基于它们的ACF有条件地操作的不同单元。

5. 发明授权

US06848041B2 Methods and apparatus for scalable instruction set architecture with dynamic compact instructions 失效
标题翻译：用于具有动态紧凑指令的可扩展指令集架构的方法和装置
公开(公告)号：US06848041B2
公开(公告)日：2005-01-25
申请号：US10424961
申请日：2003-04-28
申请人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
发明人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30178 , G06F9/30181 , G06F9/382 , G06F9/3885
摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.
摘要翻译：分层指令集架构（ISA）提供可插拔指令集功能和阵列处理器的支持。术语pluggable来自程序员的观点，并且涉及可以容易地添加到处理器架构中以用于代码密度和性能增强的指令组。本文所述的一个具体方面是独特的压缩指令集，其允许程序员能够通过任务为任务动态地创建一组压缩指令，以提高控制和并行代码密度的主要目的。这些压缩指令是可并行的，因为它们不特别地限于控制代码应用，而是可以在阵列处理器中的处理元件（PE）中执行。 ManArray系列处理器专为此动态压缩指令集功能而设计，并且还支持从一个到N个PE的可扩展阵列。此外，ManArray ISA被定义为ISA的层次结构，其允许未来指令能力的增长并且支持在指令层次结构内的多个指令的打包。

6. 发明授权

US06581152B2 Methods and apparatus for instruction addressing in indirect VLIW processors 有权
公开(公告)号：US06581152B2
公开(公告)日：2003-06-17
申请号：US10073782
申请日：2002-02-11
申请人： Edwin F. Barry , Gerald G. Pechanek
发明人： Edwin F. Barry , Gerald G. Pechanek
IPC分类号： G06F1500
CPC分类号： G06F9/382 , G06F9/30047 , G06F9/30072 , G06F9/30076 , G06F9/3017 , G06F9/32 , G06F9/3552 , G06F9/3557 , G06F9/3802 , G06F9/3842 , G06F9/3853
摘要： An indirect VLIW (iVLIW) architecture is described which contains a minimum of two instruction memories. The first instruction memory (SIM) contains short-instruction-words (SIWs) of a fixed length. The second instruction memory (VIM), contains very-long-instruction-words (VLIWs) which allow execution of multiple instructions in parallel. Each SIW may be fetched and executed as an independent instruction by one of the available execution units. A special class of SIW is used to reference the VIM indirectly to either execute or load a specified VLIW instruction (called an “XV” instruction for “eXecute VLIW”, or LV for “Load VLIW”). In these cases, the SIW instruction specifies how the location of the VLIW is to be accessed. Other aspects of this approach relate to the application of data memory addressing techniques for execution or loading of VLIWs that parallel the addressing modes used for data memory accesses. These addressing techniques provide tremendous flexibility for VLIW instruction execution.

7. 发明授权

US6167501A Methods and apparatus for manarray PE-PE switch control 有权
公开(公告)号：US6167501A
公开(公告)日：2000-12-26
申请号：US169256
申请日：1998-10-09
申请人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
发明人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80 , H04L12/56
CPC分类号： G06F15/17381 , H04L49/1553 , H04L49/201 , H04L49/3009 , H04L49/45
摘要： Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.

8. 发明授权

US06769056B2 Methods and apparatus for manifold array processing 有权
标题翻译：用于歧管阵列处理的方法和装置
公开(公告)号：US06769056B2
公开(公告)日：2004-07-27
申请号：US10254049
申请日：2002-09-24
申请人： Edwin F. Barry , Thomas L. Drabenstott , Gerald G. Pechanek , Nikos P. Pitsianis
发明人： Edwin F. Barry , Thomas L. Drabenstott , Gerald G. Pechanek , Nikos P. Pitsianis
IPC分类号： G06F1500
CPC分类号： G06F15/8023
摘要： A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.
摘要翻译：歧管阵列拓扑包括以簇排列的处理元件，节点，存储器等。集群通过集群交换机布置连接，其有利地允许组织的改变而不需要处理元件的物理重排。也实现了预先存在的阵列的典型互连数量的显着减少。快速，高效和经济高效的处理和通信带来了可扩展性的附加优势。

9. 发明授权

US06470441B1 Methods and apparatus for manifold array processing 有权
标题翻译：用于歧管阵列处理的方法和装置
公开(公告)号：US06470441B1
公开(公告)日：2002-10-22
申请号：US09707209
申请日：2000-11-06
申请人： Gerald G. Pechanek , Nikos P. Pitsianis , Edwin F. Barry , Thomas L. Drabenstott
发明人： Gerald G. Pechanek , Nikos P. Pitsianis , Edwin F. Barry , Thomas L. Drabenstott
IPC分类号： G06F1500
CPC分类号： G06F15/8023
摘要： A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.
摘要翻译：歧管阵列拓扑包括以簇排列的处理元件，节点，存储器等。集群通过集群交换机布置连接，其有利地允许组织的改变而不需要处理元件的物理重排。也实现了预先存在的阵列的典型互连数量的显着减少。快速，高效和经济高效的处理和通信带来了可扩展性的附加优势。

10. 发明授权

US06430677B2 Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision 失效
标题翻译：用于动态指令控制可重配置寄存器文件的方法和装置，具有更高的精度
公开(公告)号：US06430677B2
公开(公告)日：2002-08-06
申请号：US09796037
申请日：2001-02-28
申请人： Gerald G. Pechanek , Edwin F. Barry
发明人： Gerald G. Pechanek , Edwin F. Barry
IPC分类号： G06F1500
CPC分类号： G06F9/30036 , G06F9/30105 , G06F9/30112 , G06F9/3012 , G06F9/3016
摘要： A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.
摘要翻译：描述集成在能够进行扩展精度操作并且还能够对较低精度数据进行并行操作的指令集架构中的可重配置寄存器文件。注册文件由两个单独的文件组成，每个文件的每个文件包含与原始文件一样多的寄存器。这两半由于它们包含的寄存器地址而被指定为偶数或奇数。单个宽度和双宽度操作数得到最佳支持，而不增加寄存器文件大小，而不增加寄存器文件端口数量。还使用单独的扩展寄存器来为诸如乘法累加操作的操作提供扩展精度。

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