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1. 再颁专利

USRE38171E1 Introduction sequencer for network structure microprocessor 失效
标题翻译：介绍用于网络结构微处理器的定序器
公开(公告)号：USRE38171E1
公开(公告)日：2003-07-01
申请号：US08954438
申请日：1997-10-20
申请人： Christian Bocquet
发明人： Christian Bocquet
IPC分类号： G06F922
CPC分类号： G06F9/223
摘要： The invention concerns an instructions sequencer for microprocessor wherein the sequencer presents an architecture, a circuit conception and a presents that improves the compacity and facilitates conception and adaptation operations to different instructions sets, the sequencer having a line and column architecture and very widely produced in the form of a transistor and capacitor matrix, functioning with decoding transistors, preload transistors and a matrix for defining the phases of operating cycles.
摘要翻译：本发明涉及一种用于微处理器的指令定序器，其中定序器呈现架构，电路概念和呈现，其提高了可容许性并且促进了对不同指令集的概念和适应操作，定序器具有线和列结构，并且在晶体管和电容矩阵的形式，与解码晶体管，预加载晶体管和用于定义工作周期的相位的矩阵起作用。

2. 发明授权

US06578139B1 Processor architecture scheme which uses virtual address registers to implement different addressing modes and method therefor 有权
标题翻译：处理器架构方案使用虚拟地址寄存器来实现不同的寻址模式及其方法
公开(公告)号：US06578139B1
公开(公告)日：2003-06-10
申请号：US09691375
申请日：2000-10-18
申请人： Sumit K. Mitra , Joseph W. Triece
发明人： Sumit K. Mitra , Joseph W. Triece
IPC分类号： G06F922
CPC分类号： G06F9/30138 , G06F9/35
摘要： A processor architecture scheme which allows for encoding of multiple addressing modes through use of virtual register addresses in order to maximize number of directly addressable registers in the processor architecture scheme. A set of virtual address register locations associated with an indirect addressing pointer is reserved in memory. The number of virtual register address locations reserved is equal to a number of indirect addressing modes associated with the indirect addressing pointer. Each of the virtual register address locations initiates an indirect addressing mode to be used with the associated indirect addressing pointer when accessed.
摘要翻译：一种处理器架构方案，其允许通过使用虚拟寄存器地址对多个寻址模式进行编码，以便最大化处理器架构方案中直接可寻址寄存器的数量。与间接寻址指针相关联的一组虚拟地址寄存器位置被保留在存储器中。保留的虚拟寄存器地址位置的数量等于与间接寻址指针相关联的间接寻址模式的数量。每个虚拟寄存器地址位置启动间接寻址模式，以在访问时与相关联的间接寻址指针一起使用。

3. 发明授权

US06230253B1 Executing partial-width packed data instructions 失效
标题翻译：执行部分宽度打包的数据指令
公开(公告)号：US06230253B1
公开(公告)日：2001-05-08
申请号：US09053127
申请日：1998-03-31
申请人： Patrice Roussel , Ticky Thakkar
发明人： Patrice Roussel , Ticky Thakkar
IPC分类号： G06F922
CPC分类号： G06F9/3875 , G06F9/30014 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/30134 , G06F9/30145 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/30196 , G06F9/384 , G06F9/3885
摘要： A method and apparatus are provided for executing scalar packed data instructions. According to one aspect of the invention, a processor includes a plurality of registers, a register renaming unit coupled to the plurality of registers, a decoder coupled to the register renaming unit, and a partial-width execution unit coupled to the decoder. The register renaming unit provides an architectural register file to store packed data operands each of which include a plurality of data elements. The decoder is configured to decode a first and second set of instructions that each specify one or more registers in the architectural register file. Each of the instructions in the first set of instructions specify operations to be performed on all of the data elements stored in the one or more specified registers. In contrast, each of the instructions in the second set of instructions specify operations to be performed on only a subset of the data element stored in the one or more specified registers. The partial-width execution unit is configured to execute operations specified by either of the first or the second set of instructions.
摘要翻译：提供了一种用于执行标量打包数据指令的方法和装置。根据本发明的一个方面，处理器包括多个寄存器，耦合到多个寄存器的寄存器重命名单元，耦合到寄存器重命名单元的解码器以及耦合到解码器的部分宽度执行单元。寄存器重命名单元提供架构寄存器文件以存储打包数据操作数，每个数据操作数包括多个数据元素。解码器被配置为解码每个指定体系结构寄存器文件中的一个或多个寄存器的第一和第二组指令。第一组指令中的每个指令指定要对存储在一个或多个指定寄存器中的所有数据元素执行的操作。相反，第二组指令中的每个指令指定仅对存储在一个或多个指定寄存器中的数据元素的子集执行的操作。部分宽度执行单元被配置为执行由第一或第二组指令指定的操作。

4. 发明授权

US06526490B2 Data processing systems with process monitor 有权
标题翻译：具有过程监控的数据处理系统
公开(公告)号：US06526490B2
公开(公告)日：2003-02-25
申请号：US09801654
申请日：2001-03-09
申请人： John Alun Davies , James Frederick Moore , Peter John Stevens , Denis Vaughan Weale
发明人： John Alun Davies , James Frederick Moore , Peter John Stevens , Denis Vaughan Weale
IPC分类号： G06F922
CPC分类号： G06F9/4881 , G06F9/445 , G06F9/468 , G06F11/0757 , G06F11/3037 , G06F11/3072 , G06F12/1491 , G06F2221/2101 , G06F2221/2105
摘要： A processing system has a processor with a memory map identifying locations in a memory where data are stored, data associated with an application being stored at the same location every time an application is run. The processor runs each application during specified processing time slots. A monitor contains information as to the memory locations associated with each application and the time slots during which each application should be run. The monitor also has a register containing a keyword, which is compared with a keyword supplied by the processor 1 when it switches between user mode and supervisory mode so that the monitor denies access to memory locations associated with the other mode.
摘要翻译：处理系统具有处理器，其具有识别存储数据的存储器中的位置的存储器映射，每次应用程序运行时与存储在相同位置的应用相关联的数据。处理器在指定的处理时间段内运行每个应用程序。监视器包含关于与每个应用程序相关联的存储器位置的信息以及应该运行每个应用程序的时隙。监视器还具有包含关键字的寄存器，其与在处理器1之间切换用户模式和监视模式之间的关键字进行比较，使得监视器拒绝访问与其他模式相关联的存储器位置。

5. 发明授权

US06453407B1 Configurable long instruction word architecture and instruction set 有权
标题翻译：可配置长指令字架构和指令集
公开(公告)号：US06453407B1
公开(公告)日：2002-09-17
申请号：US09247686
申请日：1999-02-10
申请人： Yoav Lavi , Amnon Rom , Robert Knuth , Rivka Blum , Meny Yanni , Haim Granot , Anat Hershko , Georgiy Shenderovitch , Elliot Cohen , Eran Weingatren
发明人： Yoav Lavi , Amnon Rom , Robert Knuth , Rivka Blum , Meny Yanni , Haim Granot , Anat Hershko , Georgiy Shenderovitch , Elliot Cohen , Eran Weingatren
IPC分类号： G06F922
CPC分类号： G06F9/30145 , G06F9/3017 , G06F9/30174 , G06F9/3808 , G06F9/382 , G06F9/3822 , G06F9/3885
摘要： A method for executing instructions in a data processor and improvements to data processor design, which combine the advantages of regular processor architecture and Very Long Instruction Word architecture to increase execution speed and ease of programming, while reducing power consumption. Instructions each consisting of a number of operations to be performed in parallel are defined by the programmer, and their corresponding execution unit controls are generated at compile time and loaded prior to program execution into a dedicated array in processor memory. Subsequently, the programmer invokes reference instructions to call these defined instructions, and passes parameters from regular instructions in program memory. As the regular instructions propogate down the processor's pipeline, they are replaced by the appropriate controls fetched from the dedicated array in processor memory, which then go directly to the execution unit for execution. These instructions may be redefined while the program is running. In this way the processor benefits from the speed of parallel processing without the chip area and power consumption overhead of a wide program memory bus and multiple instruction decoders. A simple syntax for defining instructions, similar to that of the C programming language is presented.
摘要翻译：一种用于在数据处理器中执行指令并改进数据处理器设计的方法，其结合了常规处理器架构和超长指令字架构的优点，以提高执行速度和易于编程，同时降低功耗。由并行执行的多个操作组成的指令由程序员定义，并且它们相应的执行单元控制在编译时生成并在程序执行之前加载到处理器存储器中的专用阵列中。随后，程序员调用参考指令来调用这些定义的指令，并从程序存储器中的常规指令传递参数。由于常规指令会降低处理器的流水线，所以它们将被从处理器存储器中专用阵列中提取的相应控件所取代，然后直接执行单元执行。这些指令可能在程序运行时被重新定义。以这种方式，处理器受益于并行处理的速度，而没有宽的程序存储器总线和多个指令解码器的芯片面积和功耗开销。介绍了一种用于定义与C编程语言相似的指令的简单语法。

6. 发明授权

US06247125B1 Processor with specialized handling of repetitive operations 有权
标题翻译：具有专门处理重复操作的处理器
公开(公告)号：US06247125B1
公开(公告)日：2001-06-12
申请号：US09181795
申请日：1998-10-28
申请人： Bertrand Noel-Baron , Laurent Carre
发明人： Bertrand Noel-Baron , Laurent Carre
IPC分类号： G06F922
CPC分类号： G06F9/325
摘要： A processor that includes an instruction extraction stage, an instruction register, an instruction decoder, a first multiplexer that supplies the instruction register, and an autonomous counter with a presetting register. The first multiplexer receives the output of the extraction stage and the output of the instruction register, and the instruction decoder receives the output of the instruction register. Additionally, a first circuit produces a repetition signal if a received instruction is a repetition instruction, and a second circuit outputs a value from the received instruction to the presetting register when the received instruction is a repetition instruction. A third circuit produces an instruction execution signal that is supplied to the counter, and the first multiplexer is controlled so as to supply the instruction register based on a control output of the counter. The present invention also provides a method of handling instructions to be repeated by a processor.
摘要翻译：包括指令提取级，指令寄存器，指令解码器，提供指令寄存器的第一多路复用器以及具有预置寄存器的自主计数器的处理器。第一多路复用器接收提取级的输出和指令寄存器的输出，指令译码器接收指令寄存器的输出。另外，如果接收到的指令是重复指令，则第一电路产生重复信号，并且当接收到的指令是重复指令时，第二电路将从接收到的指令的值输出到预设寄存器。第三电路产生提供给计数器的指令执行信号，并且第一多路复用器被控制以便基于计数器的控制输出来提供指令寄存器。本发明还提供了一种处理要由处理器重复的指令的方法。

7. 发明授权

US06216223B1 Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor 有权
标题翻译：用于动态重新配置间接非常长的指令字可缩放处理器的指令流水线的方法和装置
公开(公告)号：US06216223B1
公开(公告)日：2001-04-10
申请号：US09228374
申请日：1999-01-12
申请人： Juan Guillermo Revilla , Edwin F. Barry , Patrick Rene Marchand , Gerald G. Pechanek
发明人： Juan Guillermo Revilla , Edwin F. Barry , Patrick Rene Marchand , Gerald G. Pechanek
IPC分类号： G06F922
CPC分类号： G06F9/3873 , G06F9/30058 , G06F9/30076 , G06F9/30079 , G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/3842 , G06F9/3853 , G06F9/3859 , G06F9/3867 , G06F9/3885
摘要： A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages. In addition, the dynamic reconfigurable pipeline is scalable allowing each processing element (PE) in an array of PEs to expand and compress the pipeline in synchronism allowing iVLIW operations to execute independently in each PE. This is accomplished by having distributed pipelines in operation in parallel, one in each PE and in the controller sequence processor (SP).
摘要翻译： ManArray处理器管线设计通过为需要获取VLIW的SIW提供动态可重配置的指令流水线来解决间接VLIW存储器访问问题，而不会增加分支延迟。通过仅在需要VLIW提取时引入额外的循环，本发明解决了VLIW存储器访问问题。通常，管线保持在扩展状态，直到检测到分支类型或负载VLIW存储器类型操作，将流水线返回到压缩管道操作。当检测到分支类型操作时通过压缩流水线，避免了用于分支操作的附加周期的需要。因此，与具有扩展数量的流水线级的固定管道相比，较短的压缩流水线为分支密集型控制代码提供了更高效的性能。此外，动态可重配置流水线是可扩展的，允许PE阵列中的每个处理元件（PE）同步地扩展和压缩流水线，从而允许iVLIW操作在每个PE中独立执行。这是通过并行运行分布式管道，每个PE中的一个和控制器序列处理器（SP）中实现的。

8. 发明授权

US06789185B1 Instruction control apparatus and method using micro program 失效
标题翻译：使用微程序的指令控制装置和方法
公开(公告)号：US06789185B1
公开(公告)日：2004-09-07
申请号：US09460457
申请日：1999-12-13
申请人： Norihito Gomyo , Aiichiro Inoue
发明人： Norihito Gomyo , Aiichiro Inoue
IPC分类号： G06F922
CPC分类号： G06F9/3017
摘要： A control reservation station stores the control information of a micro program to control one or more flows of an instruction process and controls each flow using the control information. A data buffer stores data to be used to control each flow and outputs the data at an appropriate timing.
摘要翻译：控制预约站存储微程序的控制信息以控制指令处理的一个或多个流程，并使用控制信息来控制每个流程。数据缓冲器存储要用于控制每个流的数据，并在适当的时刻输出数据。

9. 发明授权

US06385714B1 Data processing apparatus 有权
标题翻译：数据处理装置
公开(公告)号：US06385714B1
公开(公告)日：2002-05-07
申请号：US09154002
申请日：1998-09-16
申请人： Yasuhito Koumura , Hiroki Miura , Kenshi Matsumoto
发明人： Yasuhito Koumura , Hiroki Miura , Kenshi Matsumoto
IPC分类号： G06F922
CPC分类号： G06F9/30098 , G06F9/30123 , G06F9/3016
摘要： A data processing apparatus uses a stored-program method to execute an operation instructed by an instruction word that includes a register designation code as an operand. A plurality of work registers are identifiable by register numbers, each of a typical number of bits. A correspondence table holds at least one of the register numbers in a state corresponding to register designation codes. The codes are stored in a readable condition, and have fewer bits than the register numbers. The data processing apparatus refers to the correspondence table when executing the operation.
摘要翻译：数据处理装置使用存储程序方法来执行由包括寄存器指定码作为操作数的指令字指示的操作。多个工作寄存器可以通过寄存器号码来标识，每个工作寄存器的典型数量的位数。对应表保存与寄存器指定码对应的状态中的至少一个寄存器号。代码存储在可读的条件下，并且具有比寄存器编号少的位。数据处理装置在执行该操作时参照对应表。

10. 发明授权

US06253305B1 Microprocessor for supporting reduction of program codes in size 有权
标题翻译：支持缩小程序代码的微处理器
公开(公告)号：US06253305B1
公开(公告)日：2001-06-26
申请号：US09226791
申请日：1999-01-07
申请人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
发明人： Toshimichi Matsuzaki , Masashi Deguchi , Toshifumi Hamaguchi , Yutaka Tanase , Masahiko Matsumoto
IPC分类号： G06F922
CPC分类号： G06F9/3814 , G06F9/30149 , G06F9/30156 , G06F9/30167 , G06F9/30178 , G06F9/3802 , G06F9/3816 , G06F9/383
摘要： A microprocessor is provided for supporting reduction of codes in size, wherein instructions are extended in units of 0.5 word from a basic one word code. A word of instruction, fetched from an external memory, is transferred to a decoding register via instruction buffers and a selector both operate in units of half words, then is decoded by a decoder. A storage unit stores a state of an instruction stored in an instruction buffer. A controlling unit controls the selector so that the instructions are transferred from instruction buffers to the decoding register in units of half words based on a direction from the decoder and the states stored in the storage unit.
摘要翻译：提供了一种微处理器，用于支持尺寸减小的代码，其中指令以基本一字代码的0.5字为单位进行扩展。从外部存储器取出的指令字通过指令缓冲器传送到解码寄存器，选择器以半字为单位进行操作，然后由解码器解码。存储单元存储存储在指令缓冲器中的指令的状态。控制单元控制选择器，使得指令基于来自解码器的方向和存储在存储单元中的状态，以半字为单位从指令缓冲器传送到解码寄存器。

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