专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120173849A1 Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response 失效
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US20120173849A1
公开(公告)日：2012-07-05
申请号：US13417490
申请日：2012-03-12
申请人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
发明人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is to required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译：描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元素异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。

2. 发明授权

US08161267B2 Methods and apparatus for scalable array processor interrupt detection and response 有权
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US08161267B2
公开(公告)日：2012-04-17
申请号：US12956316
申请日：2010-11-30
申请人： Edwin Franklin Barry , Patrick R. Marchand , Gerald George Pechanek , Larry D. Larsen
发明人： Edwin Franklin Barry , Patrick R. Marchand , Gerald George Pechanek , Larry D. Larsen
IPC分类号： G06F15/76 , G06F9/305
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译：描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。

3. 发明授权

US07493474B1 Methods and apparatus for transforming, loading, and executing super-set instructions 失效
标题翻译：用于转换，加载和执行超级指令的方法和装置
公开(公告)号：US07493474B1
公开(公告)日：2009-02-17
申请号：US10985264
申请日：2004-11-10
申请人： Gerald George Pechanek , Larry D. Larsen
发明人： Gerald George Pechanek , Larry D. Larsen
IPC分类号： G06F9/30 , G06F9/40 , G06F15/00
CPC分类号： G06F9/30014 , G06F9/30036 , G06F9/30047 , G06F9/30112 , G06F9/3013 , G06F9/30149 , G06F9/30174 , G06F9/382 , G06F9/3853 , G06F9/3885
摘要： Techniques are described for loading decoded instructions and super-set instructions in a memory for later access. For loading a decoded instruction, the decoded instruction is a transformed form of an original instruction that was stored in the program memory. The transformation is from an encoded assembly level format to a binary machine level format. In one technique, the transformation mechanism is invoked by a transform and load instruction that causes an instruction retrieved from program memory to be transformed into a new language format and then loaded into a transformed instruction memory. The format of the transformed instruction may be optimized to the implementation requirements, such as improving critical path timing. The transformation of instructions may extend to other needs beyond timing path improvement, for example, requiring super-set instructions for increased functionality and improvements to instruction level parallelism. Techniques for transforming, loading, and executing super-set instructions are described.
摘要翻译：描述了用于将解码指令和超集指令加载到存储器中用于稍后访问的技术。为了加载解码指令，解码的指令是存储在程序存储器中的原始指令的变换形式。转换是从编码的汇编级别格式到二进制机器级格式。在一种技术中，变换机制由变换和加载指令调用，该指令使得从程序存储器检索的指令被转换成新的语言格式，然后被加载到经变换的指令存储器中。变换指令的格式可以根据实现要求进行优化，例如改进关键路径时序。指令的转换可以延伸到超越时序路径改进的其他需求，例如，需要用于增加功能的超集指令和指令级并行性的改进。描述用于变换，加载和执行超集指令的技术。

4. 发明授权

US6128720A Distributed processing array with component processors performing customized interpretation of instructions 失效
标题翻译：具有组件处理器的分布式处理阵列执行指令的定制解释
公开(公告)号：US6128720A
公开(公告)日：2000-10-03
申请号：US838803
申请日：1997-04-10
申请人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis
发明人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis
IPC分类号： G06F9/318 , G06F9/38 , G06F15/80 , G06F15/16
CPC分类号： G06F9/30185 , G06F15/8007 , G06F9/30189 , G06F9/3885 , G06F9/3887
摘要： A multi-processor array organization is dynamically configured by the inclusion of a configuration topology field in instructions broadcast to the processors in the array. Each of the processors in the array is capable of performing a customized data selection and storage, instruction execution, and result destination selection, by uniquely interpreting a broadcast instruction by using the identity of the processor executing the instruction. In this manner, processing elements in a large multi-processing array can be dynamically reconfigured and have their operations customized for each processor using broadcast instructions.
摘要翻译：通过在阵列中的处理器广播的指令中包括配置拓扑字段来动态配置多处理器阵列组织。通过使用执行指令的处理器的身份来唯一地解释广播指令，阵列中的每个处理器能够执行定制的数据选择和存储，指令执行和结果目的地选择。以这种方式，可以动态地重新配置大型多处理阵列中的处理元件，并使用广播指令为每个处理器定制其操作。

5. 发明授权

US06101592A Methods and apparatus for scalable instruction set architecture with dynamic compact instructions 有权
公开(公告)号：US06101592A
公开(公告)日：2000-08-08
申请号：US215081
申请日：1998-12-18
申请人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
发明人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30178 , G06F9/30181 , G06F9/382 , G06F9/3885
摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.

6. 发明授权

US5682491A Selective processing and routing of results among processors controlled by decoding instructions using mask value derived from instruction tag and processor identifier 失效
标题翻译：使用从指令标签和处理器标识符导出的掩码值，由解码指令控制的处理器之间的结果的选择性处理和路由选择
公开(公告)号：US5682491A
公开(公告)日：1997-10-28
申请号：US366140
申请日：1994-12-29
申请人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis , Daniel H. McCabe
发明人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis , Daniel H. McCabe
IPC分类号： G06F9/30 , G06F9/318 , G06F15/80 , G06F15/16
CPC分类号： G06F9/3885 , G06F15/8007 , G06F9/3012 , G06F9/30145 , G06F9/30185 , G06F9/30189 , G06F9/3887 , G06F9/3889
摘要： An array processor topology reconfiguration system and method enables processor elements in an array to dynamically reconfigure their mutual interconnection for the exchange of arithmetic results between the processors. Each processor element includes an interconnection switch which is controlled by an instruction decoder in the processor. Instructions are broadcast to all of the processors in the array. The instructions are uniquely interpreted at each respective processor in the array, depending upon the processor identity. The interpretation of the commonly broadcast instruction is uniquely performed at each processor by combining the processor identity for the executing processor, with a value in the instruction. The resulting control signals from the instruction decoder to the interconnection switch, provides for a customized linkage between the executing processor and other processors in the array.
摘要翻译：阵列处理器拓扑重构系统和方法使阵列中的处理器元件能够动态地重新配置它们的相互互连，以便在处理器之间交换算术结果。每个处理器元件包括由处理器中的指令解码器控制的互连开关。指令将广播到阵列中的所有处理器。取决于处理器标识，指令在阵列中的每个相应处理器处被唯一地解释。通过将执行处理器的处理器标识与指令中的值组合，在每个处理器处唯一地执行对广播指令的解释。从指令解码器到互连交换机的结果控制信号提供执行处理器与阵列中的其他处理器之间的定制连接。

7. 发明授权

US5371872A Method and apparatus for controlling operation of a cache memory during an interrupt 失效
标题翻译：用于在中断期间控制高速缓冲存储器的操作的方法和装置
公开(公告)号：US5371872A
公开(公告)日：1994-12-06
申请号：US783551
申请日：1991-10-28
申请人： Larry D. Larsen , David W. Nuechterlein , Kim E. O'Donnell , Lee S. Rogers , Thomas A. Sartorius , Kenneth D. Schultz , Harry I. Linzer
发明人： Larry D. Larsen , David W. Nuechterlein , Kim E. O'Donnell , Lee S. Rogers , Thomas A. Sartorius , Kenneth D. Schultz , Harry I. Linzer
IPC分类号： G06F9/46 , G06F9/48 , G06F12/08 , G06F12/10 , G06F12/12
CPC分类号： G06F12/0842 , G06F9/461
摘要： The use of a high speed cache memory may be selectively controlled when a data processing task is interrupted in response to an interrupt signal, in order to prevent the interrupt from chilling the cache when insufficient performance enhancement will be realized. Disturbing the cache memory during performance of an interrupting task is prevented, thereby increasing the hit ratio of the cache when the interrupted task is resumed. Cache control information may be incorporated into a program status vector or program status word which is loaded into a program status register on occurrence of an interrupt.
摘要翻译：当数据处理任务响应于中断信号被中断时，可以有选择地控制高速缓冲存储器的使用，以便在实现不充分的性能增强时防止中断冷却高速缓存。防止在执行中断任务期间干扰高速缓冲存储器，从而在中断的任务被恢复时增加高速缓存的命中率。高速缓存控制信息可以被并入到发生中断时加载到程序状态寄存器中的程序状态向量或程序状态字。

8. 发明申请

US20140237215A1 Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response 审中-公开
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US20140237215A1
公开(公告)日：2014-08-21
申请号：US14264263
申请日：2014-04-29
申请人： Edwin Franklin Barry , Patrick R. Marchand , Gerald George Pechanek , Larry D. Larsen
发明人： Edwin Franklin Barry , Patrick R. Marchand , Gerald George Pechanek , Larry D. Larsen
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译：描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。

9. 再颁专利

USRE40509E1 Methods and apparatus for abbreviated instruction sets adaptable to configurable processor architecture 有权
标题翻译：缩写指令集的方法和装置适应于可配置的处理器架构
公开(公告)号：USRE40509E1
公开(公告)日：2008-09-16
申请号：US10848615
申请日：2004-05-18
申请人： Gerald George Pechanek , Charles W. Kurak, Jr. , Larry D. Larsen
发明人： Gerald George Pechanek , Charles W. Kurak, Jr. , Larry D. Larsen
IPC分类号： G06F9/45
CPC分类号： G06F9/30178 , G06F8/4434 , G06F9/30156 , Y10S707/99935
摘要： An improved manifold array (ManArray) architecture addresses the problem of configurable application-spacific instruction set optimization and instruction memory reduction using an instruction abbreviation process thereby further optimizing the general ManArray architecture for application to high-volume and portablke battery-powered type of products.In the ManArray abbreviation process a standard 32-bit ManArray instruction is reduced to a smaller length instruction format, such as 14-bits. An application is first programmed using the full ManArray instruction set using the native 32-bit instructions. After the application program is completed and verified, an instruction-abbreviation tool analyzes the 32-bit application program and generates the abbreviated program using the abbreviated instructions. This instruction abbreviation process allows different program-reduction optimizations tailored for each application program. This process develops an optimized instruction set for the intended application. The abbreviated program, now located in a significantly smaller instruction memory, is functionally equivalent to the original native 32-bit application program. The abbreviated-instructions are fetched from this smaller memory and then dynamically translated into native ManArray instruction form in a sequence processor controller. Since the instruction set is now determined for the specific application. an optimized processor design can be easily produced. The system and process can be applied to native instructions having other numbers of bits and to other processing architectures.
摘要翻译：改进的歧管阵列（ManArray）架构使用指令缩写过程解决了可配置的应用空间指令集优化和指令存储器减少的问题，从而进一步优化了通用的ManArray架构，以应用于大容量和portablke电池供电类型的产品。在ManArray缩写过程中，标准的32位ManArray指令被缩减为较小长度的指令格式，例如14位。应用程序首先使用本机32位指令使用完整的ManArray指令集进行编程。应用程序完成和验证后，一个指令缩写工具分析32位应用程序，并使用缩写说明生成缩写程序。该指令缩写过程允许针对每个应用程序量身定制的不同的程序减少优化。该过程为预期应用开发了优化的指令集。缩写程序现在位于显着较小的指令存储器中，在功能上等同于原始的本机32位应用程序。缩写指令从该较小的存储器中获取，然后在序列处理器控制器中动态地转换为本地ManArray指令形式。由于现在针对具体应用确定了指令集。可以轻松制作优化的处理器设计。系统和过程可以应用于具有其他位数的本机指令和其他处理架构。

10. 发明授权

US07386710B2 Methods and apparatus for scalable array processor interrupt detection and response 有权
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US07386710B2
公开(公告)日：2008-06-10
申请号：US10931751
申请日：2004-09-01
申请人： Edwin Franklin Barry , Patrick R. Marchand , Gerald George Pechanek , Larry D. Larsen
发明人： Edwin Franklin Barry , Patrick R. Marchand , Gerald George Pechanek , Larry D. Larsen
IPC分类号： G06F9/48 , G06F9/54
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements (PEs) and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debug monitor mechanism.
摘要翻译：描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。利用这些技术，可以在包含多个处理元件（PE）和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用调试中断的通用调试方法和动态调试监视机制。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式