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1. 发明授权

US06760831B2 Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution 有权
标题翻译：在具有子字执行的基于VLIW的阵列处理器中支持条件执行的方法和装置
公开(公告)号：US06760831B2
公开(公告)日：2004-07-06
申请号：US10114652
申请日：2002-04-01
申请人： Thomas L. Drabenstott , Gerald G. Pechanek , Edwin F. Barry , Charles W. Kurak, Jr.
发明人： Thomas L. Drabenstott , Gerald G. Pechanek , Edwin F. Barry , Charles W. Kurak, Jr.
IPC分类号： G06F1580
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3885 , G06F9/3887 , G06F9/3891 , G06F15/8007
摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.
摘要翻译：使用分层一位，二位或三位编码来定义和编码通用标志（ACF）。每个添加的位提供了先前功能的超集。通过条件组合，可以避免基于复杂条件的顺序一系列条件分支，然后可以将复杂条件用于条件执行。 ACF生成和使用可以由程序员指定。通过改变受影响的标志的数量，条件操作并行性可以被广泛地变化，例如，从VLIW执行中的单处理到八进制处理，以及处理元件（PE）的阵列。多个PE可以同时生成条件信息，程序员能够基于使用处理元件之间的通信接口在不同的处理器中生成的条件来指定一个处理器中的条件执行以传送条件。多处理器阵列中的每个处理器可以独立地具有基于它们的ACF有条件地操作的不同单元。

2. 发明授权

US06954842B2 Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution 失效
标题翻译：在具有子字执行的基于VLIW的阵列处理器中支持条件执行的方法和装置
公开(公告)号：US06954842B2
公开(公告)日：2005-10-11
申请号：US10650301
申请日：2003-08-28
申请人： Thomas L. Drabenstott , Gerald G. Pechanek , Edwin F. Barry , Charles W. Kurak, Jr.
发明人： Thomas L. Drabenstott , Gerald G. Pechanek , Edwin F. Barry , Charles W. Kurak, Jr.
IPC分类号： G06F9/30 , G06F9/318 , G06F9/32 , G06F9/38 , G06F15/16 , G06F15/80 , G06F15/82 , G06F9/302
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3885 , G06F9/3887 , G06F9/3891 , G06F15/8007
摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.
摘要翻译：使用分层一位，二位或三位编码来定义和编码通用标志（ACF）。每个添加的位提供了先前功能的超集。通过条件组合，可以避免基于复杂条件的顺序一系列条件分支，然后可以将复杂条件用于条件执行。 ACF生成和使用可以由程序员指定。通过改变受影响的标志的数量，条件操作并行性可以被广泛地变化，例如，从VLIW执行中的单处理到八进制处理，以及处理元件（PE）的阵列。多个PE可以同时生成条件信息，程序员能够基于使用处理元件之间的通信接口在不同的处理器中生成的条件来指定一个处理器中的条件执行以传送条件。多处理器阵列中的每个处理器可以独立地具有基于它们的ACF有条件地操作的不同单元。

3. 发明授权

US06446191B1 Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication 有权
标题翻译：使用iVLIW PE到PE通信的高效同步MIMD操作的方法和装置
公开(公告)号：US06446191B1
公开(公告)日：2002-09-03
申请号：US09677732
申请日：2000-10-02
申请人： Gerald G. Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Carl Strube , Grayson Morris
发明人： Gerald G. Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Carl Strube , Grayson Morris
IPC分类号： G06F1516
CPC分类号： G06F9/30145 , G06F9/30167 , G06F9/3802 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization. Consequently, the term Synchronous-MIMD (SMIMD) is used to describe the present approach.
摘要翻译：使用多个并行处理器（PE）的SIMD机器，其中以有效的方式消除通信危险。使用间接超长指令字指令存储器（VIM）以及执行和分隔符指令。可以使用掩蔽机制来控制哪些PE装载有VIM。此外，优选采用操作的接收模式。在一个方面，每个PE操作以控制从其接收的PE选择的交换机。本发明解决了用于执行并行算法的更好的机器组织，其降低硬件成本和复杂性，同时保持SIMD和MIMD机器的最佳特性并最小化通信延迟。本发明为SIMD间接超长指令字（iVLIW）处理元件提供了MIMD计算自主性水平，同时保持了SIMD机器组织中使用的单一线程控制。因此，术语Synchronous-MIMD（SMIMD）用于描述当前的方法。

4. 发明授权

US6167501A Methods and apparatus for manarray PE-PE switch control 有权
公开(公告)号：US6167501A
公开(公告)日：2000-12-26
申请号：US169256
申请日：1998-10-09
申请人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
发明人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
IPC分类号： G06F15/16 , G06F15/173 , G06F15/80 , H04L12/56
CPC分类号： G06F15/17381 , H04L49/1553 , H04L49/201 , H04L49/3009 , H04L49/45
摘要： Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.

5. 发明授权

US07146487B2 Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution 有权
公开(公告)号：US07146487B2
公开(公告)日：2006-12-05
申请号：US10718415
申请日：2003-11-20
申请人： Thomas L. Drabenstott , Gerald George Pechanek , Edwin Franklin Barry , Charles W. Kurak, Jr.
发明人： Thomas L. Drabenstott , Gerald George Pechanek , Edwin Franklin Barry , Charles W. Kurak, Jr.
IPC分类号： G06F15/80
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3885 , G06F9/3887 , G06F9/3891 , G06F15/8007
摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.

6. 发明授权

US06795909B2 Methods and apparatus for ManArray PE-PE switch control 有权
标题翻译： ManArray PE-PE开关控制的方法和装置
公开(公告)号：US06795909B2
公开(公告)日：2004-09-21
申请号：US10114646
申请日：2002-04-01
申请人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
发明人： Edwin F. Barry , Gerald G. Pechanek , Thomas L. Drabenstott , Edward A. Wolff , Nikos P. Pitsianis , Grayson Morris
IPC分类号： G06F1517
CPC分类号： G06F15/17381 , H04L49/1553 , H04L49/201 , H04L49/3009 , H04L49/45
摘要： Processing element to processing element switch connection control is described using a receive model that precludes communication hazards from occurring in a synchronous MIMD mode of operation. Such control allows different communication topologies and various processing effects such as an array transpose, hypercomplement or the like to be efficiently achieved utilizing architectures, such as the manifold array processing architecture. An encoded instruction method reduces the amount of state information and setup burden on the programmer taking advantage of the recognition that the majority of algorithms will use only a small fraction of all possible mux settings available. Thus, by means of transforming the PE identification based upon a communication path specified by a PE communication instruction an efficient switch control mechanism can be used. This control mechanism allows PE register broadcast operations as well as the standard mesh and hypercube communication paths over the same interconnection network. PE to PE communication instructions PEXCHG, SPRECV and SPSEND are also defined and implemented.
摘要翻译：使用接收模型描述处理元件切换连接控制的处理元件，该接收模型排除在同步MIMD操作模式中发生通信危险。这样的控制允许利用诸如歧管阵列处理架构的架构有效地实现不同的通信拓扑和各种处理效果，例如阵列转置，超补充等。编码指令方法通过利用大多数算法仅使用所有可能的多路复用器设置的一小部分的识别来减少程序员的状态信息和设置负担的量。因此，通过基于由PE通信指令指定的通信路径变换PE标识，可以使用有效的开关控制机构。该控制机制允许PE寄存器广播操作以及相同互连网络上的标准网格和超立方体通信路径。 PE到PE通信指令PEXCHG，SPRECV和SPSEND也被定义和实现。

7. 发明授权

US6167502A Method and apparatus for manifold array processing 失效
标题翻译：用于歧管阵列处理的方法和装置
公开(公告)号：US6167502A
公开(公告)日：2000-12-26
申请号：US949122
申请日：1997-10-10
申请人： Gerald G. Pechanek , Nikos P. Pitsianis , Edwin F. Barry , Thomas L. Drabenstott
发明人： Gerald G. Pechanek , Nikos P. Pitsianis , Edwin F. Barry , Thomas L. Drabenstott
IPC分类号： G06F15/80 , G06F15/00
CPC分类号： G06F15/8023
摘要： A manifold array topology includes processing elements, nodes, memories or the like arranged in clusters. Clusters are connected by cluster switch arrangements which advantageously allow changes of organization without physical rearrangement of processing elements. A significant reduction in the typical number of interconnections for preexisting arrays is also achieved. Fast, efficient and cost effective processing and communication result with the added benefit of ready scalability.
摘要翻译：歧管阵列拓扑包括以簇排列的处理元件，节点，存储器等。集群通过集群交换机布置连接，其有利地允许组织的改变而不需要处理元件的物理重排。也实现了预先存在的阵列的典型互连数量的显着减少。快速，高效和经济高效的处理和通信带来了可扩展性的附加优势。

8. 发明授权

US6151668A Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication 有权
公开(公告)号：US6151668A
公开(公告)日：2000-11-21
申请号：US187539
申请日：1998-11-06
申请人： Gerald G. Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Carl Strube , Grayson Morris
发明人： Gerald G. Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Carl Strube , Grayson Morris
IPC分类号： G06F9/38 , G06F15/80 , G06F9/00
CPC分类号： G06F9/30145 , G06F9/30167 , G06F9/3802 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization. Consequently, the term Synchronous-MIMD (SMIMD) is used to describe the present approach.

9. 再颁专利

USRE41703E1 Methods and apparatus for efficient synchronous MIMD operations with IVLIW PE-TO-PE communication 有权
标题翻译：用于IVLIW PE-TO-PE通信的高效同步MIMD操作的方法和装置
公开(公告)号：USRE41703E1
公开(公告)日：2010-09-14
申请号：US10872995
申请日：2004-06-21
申请人： Gerald George Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Strube , Grayson Morris
发明人： Gerald George Pechanek , Thomas L. Drabenstott , Juan Guillermo Revilla , David Strube , Grayson Morris
IPC分类号： G06F15/16
CPC分类号： G06F9/30145 , G06F9/30167 , G06F9/3802 , G06F9/3853 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： A SIMD machine employing a plurality of parallel processor (PEs) in which communications hazards are eliminated in an efficient manner. An indirect Very Long Instruction Word instruction memory (VIM) is employed along with execute and delimiter instructions. A masking mechanism may be employed to control which PEs have their VIMs loaded. Further, a receive model of operation is preferably employed. In one aspect, each PE operates to control a switch that selects from which PE it receives. The present invention addresses a better machine organization for execution of parallel algorithms that reduces hardware cost and complexity while maintaining the best characteristics of both SIMD and MIMD machines and minimizing communication latency. This invention brings a level of MIMD computational autonomy to SIMD indirect Very Long Instruction Word (iVLIW) processing elements while maintaining the single thread of control used in the SIMD machine organization. Consequently, the term Synchronous-MIMD (SMIMD) is used to describe the present approach.
摘要翻译：使用多个并行处理器（PE）的SIMD机器，其中以有效的方式消除通信危险。使用间接超长指令字指令存储器（VIM）以及执行和分隔符指令。可以使用掩蔽机制来控制哪些PE装载有VIM。此外，优选采用操作的接收模式。在一个方面，每个PE操作以控制从其接收的PE选择的交换机。本发明解决了用于执行并行算法的更好的机器组织，其降低硬件成本和复杂性，同时保持SIMD和MIMD机器的最佳特性并最小化通信延迟。本发明为SIMD间接超长指令字（iVLIW）处理元件提供了MIMD计算自主性水平，同时保持了SIMD机器组织中使用的单一线程控制。因此，术语Synchronous-MIMD（SMIMD）用于描述当前的方法。

10. 发明授权

US07010668B2 Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution 失效
公开(公告)号：US07010668B2
公开(公告)日：2006-03-07
申请号：US10650340
申请日：2003-08-28
申请人： Thomas L. Drabenstott , Gerald G. Penchanek , Edwin F. Barry , Charles W. Kurak, Jr.
发明人： Thomas L. Drabenstott , Gerald G. Penchanek , Edwin F. Barry , Charles W. Kurak, Jr.
IPC分类号： G06F15/76 , G06F15/80
CPC分类号： G06F9/30094 , G06F9/30036 , G06F9/30072 , G06F9/30181 , G06F9/3842 , G06F9/3885 , G06F9/3887 , G06F9/3891 , G06F15/8007
摘要： General purpose flags (ACFs) are defined and encoded utilizing a hierarchical one-, two- or three-bit encoding. Each added bit provides a superset of the previous functionality. With condition combination, a sequential series of conditional branches based on complex conditions may be avoided and complex conditions can then be used for conditional execution. ACF generation and use can be specified by the programmer. By varying the number of flags affected, conditional operation parallelism can be widely varied, for example, from mono-processing to octal-processing in VLIW execution, and across an array of processing elements (PE)s. Multiple PEs can generate condition information at the same time with the programmer being able to specify a conditional execution in one processor based upon a condition generated in a different processor using the communications interface between the processing elements to transfer the conditions. Each processor in a multiple processor array may independently have different units conditionally operate based upon their ACFs.

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