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1. 发明授权

US06848041B2 Methods and apparatus for scalable instruction set architecture with dynamic compact instructions 失效
标题翻译：用于具有动态紧凑指令的可扩展指令集架构的方法和装置
公开(公告)号：US06848041B2
公开(公告)日：2005-01-25
申请号：US10424961
申请日：2003-04-28
申请人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
发明人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30178 , G06F9/30181 , G06F9/382 , G06F9/3885
摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.
摘要翻译：分层指令集架构（ISA）提供可插拔指令集功能和阵列处理器的支持。术语pluggable来自程序员的观点，并且涉及可以容易地添加到处理器架构中以用于代码密度和性能增强的指令组。本文所述的一个具体方面是独特的压缩指令集，其允许程序员能够通过任务为任务动态地创建一组压缩指令，以提高控制和并行代码密度的主要目的。这些压缩指令是可并行的，因为它们不特别地限于控制代码应用，而是可以在阵列处理器中的处理元件（PE）中执行。 ManArray系列处理器专为此动态压缩指令集功能而设计，并且还支持从一个到N个PE的可扩展阵列。此外，ManArray ISA被定义为ISA的层次结构，其允许未来指令能力的增长并且支持在指令层次结构内的多个指令的打包。

2. 发明授权

US06557094B2 Methods and apparatus for scalable instruction set architecture with dynamic compact instructions 有权
公开(公告)号：US06557094B2
公开(公告)日：2003-04-29
申请号：US09969077
申请日：2001-09-28
申请人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
发明人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
IPC分类号： G06F1580
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30178 , G06F9/30181 , G06F9/382 , G06F9/3885
摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.

3. 发明授权

US06321322B1 Methods and apparatus for scalable instruction set architecture with dynamic compact instructions 有权
标题翻译：用于具有动态紧凑指令的可扩展指令集架构的方法和装置
公开(公告)号：US06321322B1
公开(公告)日：2001-11-20
申请号：US09543473
申请日：2000-04-05
申请人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
发明人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
IPC分类号： G06F1580
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30178 , G06F9/30181 , G06F9/382 , G06F9/3885
摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.
摘要翻译：分层指令集架构（ISA）提供可插拔指令集功能和阵列处理器的支持。术语pluggable来自程序员的观点，并且涉及可以容易地添加到处理器架构中以用于代码密度和性能增强的指令组。本文所述的一个具体方面是独特的压缩指令集，其允许程序员能够通过任务为任务动态地创建一组压缩指令，以提高控制和并行代码密度的主要目的。这些压缩指令是可并行的，因为它们不特别地限于控制代码应用，而是可以在阵列处理器中的处理元件（PE）中执行。 ManArray系列处理器专为此动态压缩指令集功能而设计，并且还支持从一个到N个PE的可扩展阵列。此外，ManArray ISA被定义为ISA的层次结构，其允许未来指令能力的增长并且支持在指令层次结构内的多个指令的打包。

4. 发明授权

US06101592A Methods and apparatus for scalable instruction set architecture with dynamic compact instructions 有权
公开(公告)号：US06101592A
公开(公告)日：2000-08-08
申请号：US215081
申请日：1998-12-18
申请人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
发明人： Gerald G. Pechanek , Edwin F. Barry , Juan Guillermo Revilla , Larry D. Larsen
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38 , G06F15/80
CPC分类号： G06F9/3822 , G06F9/30145 , G06F9/30149 , G06F9/30178 , G06F9/30181 , G06F9/382 , G06F9/3885
摘要： A hierarchical instruction set architecture (ISA) provides pluggable instruction set capability and support of array processors. The term pluggable is from the programmer's viewpoint and relates to groups of instructions that can easily be added to a processor architecture for code density and performance enhancements. One specific aspect addressed herein is the unique compacted instruction set which allows the programmer the ability to dynamically create a set of compacted instructions on a task by task basis for the primary purpose of improving control and parallel code density. These compacted instructions are parallelizable in that they are not specifically restricted to control code application but can be executed in the processing elements (PEs) in an array processor. The ManArray family of processors is designed for this dynamic compacted instruction set capability and also supports a scalable array of from one to N PEs. In addition, the ManArray ISA is defined as a hierarchy of ISAs which allows for future growth in instruction capability and supports the packing of multiple instructions within a hierarchy of instructions.

5. 发明授权

US06397324B1 Accessing tables in memory banks using load and store address generators sharing store read port of compute register file separated from address register file 有权
标题翻译：使用加载和存储地址生成器访问存储库中的表，共享存储与地址寄存器文件分离的计算寄存器文件的读取端口
公开(公告)号：US06397324B1
公开(公告)日：2002-05-28
申请号：US09596103
申请日：2000-06-16
申请人： Edwin Frank Barry , Charles W. Kurak, Jr. , Gerald G. Pechanek , Larry D. Larsen
发明人： Edwin Frank Barry , Charles W. Kurak, Jr. , Gerald G. Pechanek , Larry D. Larsen
IPC分类号： G06F9312
CPC分类号： G06F9/3004 , G06F9/30112 , G06F9/3012 , G06F9/3013 , G06F9/3885 , H03M7/425
摘要： A very long instruction word (VLIW) processor typically requires a large number of register file ports due to the parallel execution of the sub-instructions comprising the VLIW. By splitting a general purpose register file into separate address and compute register files, the number of compute register file ports is significantly reduced. This reduction is particularly evident when multiple load and store execution units with indexed addressing modes are supported. The implication is that a faster register file and dedicated address registers are achieved in the programming model. The savings comes at the cost of providing support for data movement between the compute register file and the address register file. In addition, address arithmetic, table look-up, and store to table functions are desirable functions that cannot be obviously obtained when the address registers are separated from the compute registers. The present approach provides an efficient mechanism for supporting these functions while maintaining separate compute and address register files.
摘要翻译：由于并行执行包括VLIW的子指令，很长的指令字（VLIW）处理器通常需要大量的寄存器文件端口。通过将通用寄存器文件分割成单独的地址和计算寄存器文件，计算寄存器文件端口的数量大大减少。当支持具有索引寻址模式的多个加载和存储执行单元时，这种减少尤其明显。这意味着在编程模型中实现了更快的寄存器文件和专用地址寄存器。节省成本是为计算寄存器文件和地址寄存器文件之间的数据移动提供支持。此外，地址算术，表查找和存储到表函数是当地址寄存器与计算寄存器分离时不能明显获得的所需函数。本方法提供了一种支持这些功能的有效机制，同时保持单独的计算和地址寄存器文件。

6. 发明申请

US20080222333A1 Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response 有权
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US20080222333A1
公开(公告)日：2008-09-11
申请号：US12120543
申请日：2008-05-14
申请人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
发明人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
IPC分类号： G06F13/24 , G06F9/30 , G06F9/312
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译：描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。

7. 发明授权

US06842811B2 Methods and apparatus for scalable array processor interrupt detection and response 失效
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US06842811B2
公开(公告)日：2005-01-11
申请号：US09791256
申请日：2001-02-23
申请人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
发明人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
IPC分类号： G06F9/00 , G06F9/38 , G06F9/48 , G06F13/24 , G06F13/26
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements (PEs) and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debug interrupts and a dynamic debuts monitor mechanism.
摘要翻译：描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。利用这些技术，可以在包含多个处理元件（PE）和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元件异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用调试中断的通用调试方法和动态初始化监视机制。

8. 发明授权

US5659785A Array processor communication architecture with broadcast processor instructions 失效
标题翻译：具有广播处理器指令的阵列处理器通信架构
公开(公告)号：US5659785A
公开(公告)日：1997-08-19
申请号：US386384
申请日：1995-02-10
申请人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis
发明人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis
IPC分类号： G06F15/16 , G06F15/173 , G06F15/177 , G06F15/80
CPC分类号： G06F15/17381
摘要： A plurality of processor elements (PEs) are connected in a duster by a common instruction bus to a sequencing control unit with its associated instruction memory. Each PE has data buses connected to at least its four nearest PE neighbors, referred to as its North, South, East and West PE neighbors. Each PE also has a general purpose register file containing several operand registers. A common instruction is fetched from the instruction memory by the sequencing control unit and broadcast over the instruction bus to each PE in the cluster. The instruction includes an upcode value that controls the arithmetic or logical operation performed by an execution unit in the PE on one or more operands in the register file. A switch is included in each PE to interconnect it with a first PE neighbor as the destination to which the result from the execution unit is sent. The broadcast instruction includes a destination field that controls the switch in the PE, to dynamically select the destination neighbor PE to which the result is sent. Further, the broadcast instruction includes a target field that controls the switch in the PE, to dynamically select the operand register in the register file of the PE, to which another result received from another neighbor PE in the cluster is stored. In this manner, the instruction broadcast to all the PEs in the cluster, dynamically controls the communication of operands and results between the PEs in the cluster, in a single instruction, multiple data processor array.
摘要翻译：多个处理器元件（PE）通过公共指令总线连接到除尘器中，其具有与其相关联的指令存储器的排序控制单元。每个PE都有数据总线连接到至少其四个最近的PE邻居，称为其北，南，东和西PE邻居。每个PE还有一个包含多个操作数寄存器的通用寄存器文件。通过排序控制单元从指令存储器取出通用指令，并通过指令总线广播到集群中的每个PE。该指令包括一个上限值，其控制由PE中的执行单元在寄存器文件中的一个或多个操作数上执行的算术或逻辑操作。每个PE中包括一个交换机，将其与第一个PE邻居进行互连，作为发送执行单元的结果的目的地。广播指令包括控制PE中的交换机的目的地字段，动态地选择发送结果的目的地邻居PE。此外，广播指令包括控制PE中的交换机的目标字段，动态地选择PE的寄存器文件中的操作数寄存器，存储从群集中的另一个邻居PE接收到的另一结果。以这种方式，向集群中的所有PE广播的指令在单个指令，多数据处理器阵列中动态地控制集群中的PE之间的操作数和结果的通信。

9. 发明申请

US20120173849A1 Methods and Apparatus for Scalable Array Processor Interrupt Detection and Response 失效
标题翻译：用于可扩展阵列处理器中断检测和响应的方法和装置
公开(公告)号：US20120173849A1
公开(公告)日：2012-07-05
申请号：US13417490
申请日：2012-03-12
申请人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
发明人： Edwin Frank Barry , Patrick R. Marchand , Gerald G. Pechanek , Larry D. Larsen
IPC分类号： G06F9/38 , G06F9/312
CPC分类号： G06F9/3865 , G06F9/30058 , G06F9/3861 , G06F9/4812 , G06F11/27 , G06F13/26 , Y02D10/14 , Y02D10/24
摘要： Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is to required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
摘要翻译：描述了可扩展流水线阵列处理器环境中的中断检测和响应的硬件和软件技术。利用这些技术，可以在包含多个处理元件和分布式存储器和寄存器文件的高度并行的可扩展流水线阵列处理中维持具有中断的顺序程序执行模型。当发生中断时，接口信号提供给所有PE，以支持每个PE中的独立中断操作，取决于中断前的本地PE指令序列。支持处理/元素异常中断，并为需要实时信号处理的嵌入式系统提供低延迟中断处理。此外，使用分层中断结构，允许使用初次中断的通用调试方法和动态登场监视机制。

10. 发明授权

US6128720A Distributed processing array with component processors performing customized interpretation of instructions 失效
标题翻译：具有组件处理器的分布式处理阵列执行指令的定制解释
公开(公告)号：US6128720A
公开(公告)日：2000-10-03
申请号：US838803
申请日：1997-04-10
申请人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis
发明人： Gerald G. Pechanek , Larry D. Larsen , Clair John Glossner , Stamatis Vassiliaadis
IPC分类号： G06F9/318 , G06F9/38 , G06F15/80 , G06F15/16
CPC分类号： G06F9/30185 , G06F15/8007 , G06F9/30189 , G06F9/3885 , G06F9/3887
摘要： A multi-processor array organization is dynamically configured by the inclusion of a configuration topology field in instructions broadcast to the processors in the array. Each of the processors in the array is capable of performing a customized data selection and storage, instruction execution, and result destination selection, by uniquely interpreting a broadcast instruction by using the identity of the processor executing the instruction. In this manner, processing elements in a large multi-processing array can be dynamically reconfigured and have their operations customized for each processor using broadcast instructions.
摘要翻译：通过在阵列中的处理器广播的指令中包括配置拓扑字段来动态配置多处理器阵列组织。通过使用执行指令的处理器的身份来唯一地解释广播指令，阵列中的每个处理器能够执行定制的数据选择和存储，指令执行和结果目的地选择。以这种方式，可以动态地重新配置大型多处理阵列中的处理元件，并使用广播指令为每个处理器定制其操作。

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