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1. 发明授权

US06216223B1 Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor 有权
标题翻译：用于动态重新配置间接非常长的指令字可缩放处理器的指令流水线的方法和装置
公开(公告)号：US06216223B1
公开(公告)日：2001-04-10
申请号：US09228374
申请日：1999-01-12
申请人： Juan Guillermo Revilla , Edwin F. Barry , Patrick Rene Marchand , Gerald G. Pechanek
发明人： Juan Guillermo Revilla , Edwin F. Barry , Patrick Rene Marchand , Gerald G. Pechanek
IPC分类号： G06F922
CPC分类号： G06F9/3873 , G06F9/30058 , G06F9/30076 , G06F9/30079 , G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/3842 , G06F9/3853 , G06F9/3859 , G06F9/3867 , G06F9/3885
摘要： A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages. In addition, the dynamic reconfigurable pipeline is scalable allowing each processing element (PE) in an array of PEs to expand and compress the pipeline in synchronism allowing iVLIW operations to execute independently in each PE. This is accomplished by having distributed pipelines in operation in parallel, one in each PE and in the controller sequence processor (SP).
摘要翻译： ManArray处理器管线设计通过为需要获取VLIW的SIW提供动态可重配置的指令流水线来解决间接VLIW存储器访问问题，而不会增加分支延迟。通过仅在需要VLIW提取时引入额外的循环，本发明解决了VLIW存储器访问问题。通常，管线保持在扩展状态，直到检测到分支类型或负载VLIW存储器类型操作，将流水线返回到压缩管道操作。当检测到分支类型操作时通过压缩流水线，避免了用于分支操作的附加周期的需要。因此，与具有扩展数量的流水线级的固定管道相比，较短的压缩流水线为分支密集型控制代码提供了更高效的性能。此外，动态可重配置流水线是可扩展的，允许PE阵列中的每个处理元件（PE）同步地扩展和压缩流水线，从而允许iVLIW操作在每个PE中独立执行。这是通过并行运行分布式管道，每个PE中的一个和控制器序列处理器（SP）中实现的。

2. 发明授权

US06775766B2 Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor 有权
标题翻译：用于动态重新配置间接非常长的指令字可缩放处理器的指令流水线的方法和装置
公开(公告)号：US06775766B2
公开(公告)日：2004-08-10
申请号：US09796040
申请日：2001-02-28
申请人： Juan Guillermo Revilla , Edwin F. Barry , Patrick Rene Marchand , Gerald G. Pechanek
发明人： Juan Guillermo Revilla , Edwin F. Barry , Patrick Rene Marchand , Gerald G. Pechanek
IPC分类号： G06F922
CPC分类号： G06F9/3873 , G06F9/30058 , G06F9/30076 , G06F9/30079 , G06F9/30181 , G06F9/30189 , G06F9/3802 , G06F9/3842 , G06F9/3853 , G06F9/3859 , G06F9/3867 , G06F9/3885
摘要： A ManArray processor pipeline design addresses an indirect VLIW memory access problem without increasing branch latency by providing a dynamically reconfigurable instruction pipeline for SIWs requiring a VLIW to be fetched. By introducing an additional cycle in the pipeline only when a VLIW fetch is required, the present invention solves the VLIW memory access problem. The pipeline stays in an expanded state, in general, until a branch type or load VLIW memory type operation is detected returning the pipeline to a compressed pipeline operation. By compressing the pipeline when a branch type operation is detected, the need for an additional cycle for the branch operation is avoided. Consequently, the shorter compressed pipeline provides more efficient performance for branch intensive control code as compared to a fixed pipeline with an expanded number of pipeline stages. In addition, the dynamic reconfigurable pipeline is scalable allowing each processing element (PE) in an array of PEs to expand and compress the pipeline in synchronism allowing iVLIW operations to execute independently in each PE. This is accomplished by having distributed pipelines in operation in parallel, one in each PE and in the controller sequence processor (SP).
摘要翻译： ManArray处理器管线设计通过为需要获取VLIW的SIW提供动态可重配置的指令流水线来解决间接VLIW存储器访问问题，而不会增加分支延迟。通过仅在需要VLIW提取时引入额外的循环，本发明解决了VLIW存储器访问问题。通常，管线保持在扩展状态，直到检测到分支类型或负载VLIW存储器类型操作，将流水线返回到压缩管道操作。当检测到分支类型操作时通过压缩流水线，避免了用于分支操作的附加周期的需要。因此，与具有扩展数量的流水线级的固定管道相比，较短的压缩流水线为分支密集型控制代码提供了更高效的性能。此外，动态可重配置流水线是可扩展的，允许PE阵列中的每个处理元件（PE）同步地扩展和压缩流水线，从而允许iVLIW操作在每个PE中独立执行。这是通过并行运行分布式管道，每个PE中的一个和控制器序列处理器（SP）中实现的。

3. 发明授权

US07024540B2 Methods and apparatus for establishing port priority functions in a VLIW processor 失效
标题翻译：在VLIW处理器中建立端口优先功能的方法和装置
公开(公告)号：US07024540B2
公开(公告)日：2006-04-04
申请号：US10695071
申请日：2003-10-28
申请人： Edwin Frank Barry , Edward A. Wolff , Patrick Rene Marchand , David Carl Strube
发明人： Edwin Frank Barry , Edward A. Wolff , Patrick Rene Marchand , David Carl Strube
IPC分类号： G06F12/00
CPC分类号： G06F9/30141 , G06F9/30003 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/3016 , G06F9/3838 , G06F9/3853 , G06F9/3885
摘要： Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1. Other unique capabilities result from the present approach to assigning port priorities that improve the performance of the ManArray indirect VLIW processor.
摘要翻译：端口优先级定义在32位字，16位半字和8位字节的基础上，用于将写使能信号控制到计算寄存器文件（CRF）。使用歧管阵列（ManArray）可重配置寄存器文件，可以将双字64位和单字32位数据类型指令与其他双字，单字，半字或字节数据混合类型的指令在相同的很长的指令字（VLIW）内。通过在VLIW执行期间解决冲突的字节，半字或字的写入优先级冲突，可以使部分操作完成，从而提供有用的功能。例如，对于32位寄存器R 0的半字H 0部分的加载半字可以优先完成其操作，而寄存器对R 0和R 1的64位移位将完成其操作在64位寄存器R 0和R 1的非冲突半字部分上。其他独特功能来自本方法分配端口优先级，以提高ManArray间接VLIW处理器的性能。

4. 发明授权

US06654870B1 Methods and apparatus for establishing port priority functions in a VLIW processor 有权
标题翻译：在VLIW处理器中建立端口优先功能的方法和装置
公开(公告)号：US06654870B1
公开(公告)日：2003-11-25
申请号：US09598084
申请日：2000-06-21
申请人： Edwin Frank Barry , Edward A. Wolff , Patrick Rene Marchand , David Carl Strube
发明人： Edwin Frank Barry , Edward A. Wolff , Patrick Rene Marchand , David Carl Strube
IPC分类号： G06F938
CPC分类号： G06F9/30141 , G06F9/30003 , G06F9/30036 , G06F9/30112 , G06F9/3013 , G06F9/3016 , G06F9/3838 , G06F9/3853 , G06F9/3885
摘要： Port priorities are defined on a 32-bit word, 16-bit half-word, and 8-bit byte basis to control the write enable signals to a compute register file (CRF). With a manifold array (ManArray) reconfigurable register file, it is possible to have double-word 64-bit and single word 32-bit data-type instructions mixed with other double-word, single-word, half-word, or byte data-type instructions within the same very long instruction word (VLIW). By resolving a write priority conflict on the byte, half-word, or word that is in conflict during the VLIW execution, it is possible to have partial operations complete that provide a useful function. For. example, a load half-word to the half-word H0 portion of a 32-bit register R0 can have priority to complete its operation while a 64-bit shift of the register pair R0 and R1 will complete its operation on the non-conflicting half-word portions of the 64-bit register R0 and R1. Other unique capabilities result from the present approach to assigning port priorities that improve the performance of the ManArray indirect VLIW processor.
摘要翻译：端口优先级定义在32位字，16位半字和8位字节的基础上，用于将写使能信号控制到计算寄存器文件（CRF）。使用歧管阵列（ManArray）可重配置寄存器文件，可以将双字64位和单字32位数据类型指令与其他双字，单字，半字或字节数据混合类型的指令在相同的很长的指令字（VLIW）内。通过在VLIW执行期间解决冲突的字节，半字或字的写入优先级冲突，可以使部分操作完成，从而提供有用的功能。对于。例如，到32位寄存器R0的半字H0部分的加载半字可以优先完成其操作，而寄存器对R0和R1的64位移位将完成其在非冲突的操作 64位寄存器R0和R1的半字部分。目前的分配端口优先级方法的其他独特功能来自于提高ManArray间接VLIW处理器的性能。

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