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1. 发明授权

US07130944B2 Chip-to-chip communication system using an ac-coupled bus and devices employed in same 失效
公开(公告)号：US07130944B2
公开(公告)日：2006-10-31
申请号：US11021207
申请日：2004-12-23
申请人： Donald V. Perino , Haw-Jyh Liaw , Alfredo Moncayo , Kevin Donnelly , Richard M. Barth , Bruno W. Garlepp
发明人： Donald V. Perino , Haw-Jyh Liaw , Alfredo Moncayo , Kevin Donnelly , Richard M. Barth , Bruno W. Garlepp
IPC分类号： G06F13/00
CPC分类号： H01L23/48 , G06F13/423 , H01L2224/48091 , H01L2224/48247 , H01L2924/12032 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.

2. 发明授权

US06496889B1 Chip-to-chip communication system using an ac-coupled bus and devices employed in same 失效
标题翻译：使用交流耦合总线的芯片到芯片通信系统及其使用的器件
公开(公告)号：US06496889B1
公开(公告)日：2002-12-17
申请号：US09398251
申请日：1999-08-16
申请人： Donald V. Perino , Haw-Jyh Liaw , Alfredo Moncayo , Kevin Donnelly , Richard M. Barth , Bruno W. Garlepp
发明人： Donald V. Perino , Haw-Jyh Liaw , Alfredo Moncayo , Kevin Donnelly , Richard M. Barth , Bruno W. Garlepp
IPC分类号： G06F1314
CPC分类号： H01L23/48 , G06F13/423 , H01L2224/48091 , H01L2224/48247 , H01L2924/12032 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： A chip-to-chip communication system and interface technique. A master and at least two devices are interconnected with a signal line of a high speed bus. A capacitive coupling element, for example a diode, is employed to capacitively couple the interface of the device to the signal line. By employing the capacitive coupling element, along with a suitable signaling technique which supports capacitive information transfer, high speed rates of information transfer between the master and device over the signal line are achieved.
摘要翻译：一种芯片到芯片的通信系统和接口技术。主机和至少两个设备与高速总线的信号线相互连接。采用电容耦合元件，例如二极管，将器件的接口电容耦合到信号线。通过采用电容耦合元件以及支持电容信息传输的合适的信令技术，实现了信号线上的主设备和设备之间的高速信息传送速率。

3. 发明授权

US06854030B2 Integrated circuit device having a capacitive coupling element 失效
标题翻译：具有电容耦合元件的集成电路器件
公开(公告)号：US06854030B2
公开(公告)日：2005-02-08
申请号：US10287100
申请日：2002-11-04
申请人： Donald V. Perino , Haw-Jyh Liaw , Alfredo Moncayo , Kevin Donnelly , Richard M. Barth , Bruno W. Garlepp
发明人： Donald V. Perino , Haw-Jyh Liaw , Alfredo Moncayo , Kevin Donnelly , Richard M. Barth , Bruno W. Garlepp
IPC分类号： G06F13/14 , G06F13/42 , G11C8/00 , H01L23/48
CPC分类号： H01L23/48 , G06F13/423 , H01L2224/48091 , H01L2224/48247 , H01L2924/12032 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： An integrated circuit memory device that include an input receiver, an output driver, and a capacitive coupling element. The capacitive coupling element includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is coupled to the input receiver and the output driver, an the second capacitor electrode couples to an external signal line. Delay modulated data is received by the input receiver from the external signal line via the capacitive coupling element.
摘要翻译：一种集成电路存储器件，包括输入接收器，输出驱动器和电容耦合元件。电容耦合元件包括第一电容器电极和第二电容器电极。第一电容器电极耦合到输入接收器和输出驱动器，第二电容器电极耦合到外部信号线。延迟调制数据由输入接收器经由电容耦合元件从外部信号线接收。

4. 发明授权

US06687780B1 Expandable slave device system 失效
标题翻译：可扩展的从设备系统
公开(公告)号：US06687780B1
公开(公告)日：2004-02-03
申请号：US09706238
申请日：2000-11-02
申请人： Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
发明人： Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
IPC分类号： G06F1340
CPC分类号： G06F13/4072 , G06F13/4086 , G06F13/4243
摘要： A bus system for use with addressable memory has a global bus of uni-directional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus. First and second global bus terminators are coupled to the first and second ends of the global bus, respectively. One or more subsystems are connected in parallel to each other and to the master device via the global bus. Each subsystem includes a local bus, one or more slave devices coupled to the local bus, a write buffer that receives incoming signals from the master device via the global bus and transmits the incoming signals to the one or more slave devices via the local bus, and a read buffer that receives outgoing signals from the one or more slave devices via the local bus and transmits the outgoing signals to the master device via the global bus.
摘要翻译：与可寻址存储器一起使用的总线系统具有单向信号线的全局总线。全球总线有一个第一端和一端。主设备向全局总线发送数据并从全局总线接收数据。第一和第二全局总线终端分别耦合到全局总线的第一和第二端。一个或多个子系统通过全局总线彼此并联连接到主设备。每个子系统包括本地总线，耦合到本地总线的一个或多个从设备，经由全局总线接收来自主设备的输入信号的写入缓冲器，并且经由本地总线将输入信号发送到一个或多个从设备，以及读取缓冲器，其经由本地总线从一个或多个从设备接收输出信号，并经由全局总线将输出信号发送到主设备。

5. 发明授权

US07536494B2 Expandable slave device system with buffered subsystems 有权
标题翻译：具有缓冲子系统的可扩展从属设备系统
公开(公告)号：US07536494B2
公开(公告)日：2009-05-19
申请号：US11752242
申请日：2007-05-22
申请人： Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
发明人： Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
IPC分类号： G06F13/36
CPC分类号： G06F13/4072 , G06F13/4086 , G06F13/4243
摘要： A system includes a first bus, a master device coupled to the first bus, and one or more subsystems coupled to the first bus. A respective subsystem includes a second bus, one or more slave devices coupled to the second bus, a write buffer to receive incoming signals from the master device via the first bus and to transmit signals to the one or more slave devices via the second bus in response to the incoming signals, and a read buffer to receive outgoing signals from the one or more slave devices via the second bus and to transmit signals to the master device via the first bus in response to the outgoing signals.
摘要翻译：系统包括第一总线，耦合到第一总线的主设备和耦合到第一总线的一个或多个子系统。相应的子系统包括第二总线，耦合到第二总线的一个或多个从设备，写入缓冲器，用于经由第一总线接收来自主设备的输入信号，以及经由第二总线将信号发送到一个或多个从设备响应于输入信号，以及读缓冲器，用于经由第二总线接收来自一个或多个从设备的输出信号，并响应于输出信号经由第一总线向主设备发送信号。

6. 发明授权

US07222209B2 Expandable slave device system 有权
标题翻译：可扩展的从设备系统
公开(公告)号：US07222209B2
公开(公告)日：2007-05-22
申请号：US10738293
申请日：2003-12-16
申请人： Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
发明人： Bruno W. Garlepp , Richard M. Barth , Kevin S. Donnelly , Ely K. Tsern , Craig E. Hampel , Jeffrey D. Mitchell , James A. Gasbarro , Billy W. Garrett, Jr. , Fredrick A. Ware , Donald V. Perino
IPC分类号： G06F13/14
CPC分类号： G06F13/4072 , G06F13/4086 , G06F13/4243
摘要： A bus system for use with addressable memory has a global bus of bidirectional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus at the first end. A global bus terminator is coupled to the global bus at the second end. One or more slave devices, including a last slave device at a furthest distance from the master device, each includes an active terminator coupled to at least some of the bidirectional signal lines of the global bus. The active terminator of only the last slave device is enabled.
摘要翻译：与可寻址存储器一起使用的总线系统具有双向信号线的全局总线。全球总线有一个第一端和一端。主设备在第一端向全局总线发送数据并从其接收数据。全局总线终端器在第二端耦合到全局总线。一个或多个从设备，包括与主设备最远距离的最后一个从设备，每个包括耦合到全局总线的至少一些双向信号线的有源终端器。只有最后一个从设备的活动终端才能使能。

7. 发明授权

US06530062B1 Active impedance compensation 失效
标题翻译：有源阻抗补偿
公开(公告)号：US06530062B1
公开(公告)日：2003-03-04
申请号：US09523520
申请日：2000-03-10
申请人： Haw-Jyh Liaw , Donald V. Perino , Pak Shing Chau , Kevin S. Donnelly
发明人： Haw-Jyh Liaw , Donald V. Perino , Pak Shing Chau , Kevin S. Donnelly
IPC分类号： G06F1750
CPC分类号： G06F13/4086
摘要： Active impedance compensation is accomplished in a bus system by means of a variable capacitor element associated with a connection circuit between system slave devices and an impedance balanced channel. The variable capacitor elements may be programmed using a control value determined by actively exercising the channel with a telemetry signal and evaluating the resulting signal reflections which are indicative of the impedance discontinuities on the channel.
摘要翻译：有源阻抗补偿通过与系统从设备之间的连接电路和阻抗平衡通道相关联的可变电容器元件在总线系统中完成。可变电容器元件可以使用通过用遥测信号主动地运行通道所确定的控制值进行编程，并且评估指示通道上的阻抗不连续性的结果信号反射。

8. 发明授权

US6067594A High frequency bus system 失效
标题翻译：高频总线系统
公开(公告)号：US6067594A
公开(公告)日：2000-05-23
申请号：US938084
申请日：1997-09-26
申请人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
发明人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
IPC分类号： G06F13/00 , G06F13/40 , G11C5/00 , G11C5/06 , H05K1/02 , H05K1/14 , H05K7/14
CPC分类号： G11C5/063 , G06F13/1684 , G06F13/4086 , G06F13/409 , G06F13/4247 , G11C5/04 , H05K1/0246 , H05K1/0248 , H05K7/1459 , G11C7/1048 , H05K1/023 , H05K1/14 , H05K2201/044 , H05K2201/09263 , H05K2201/10022 , H05K2201/10159 , H05K2201/10689
摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.
摘要翻译：尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。高频总线系统还包括没有与其连接的设备的第二总线段。第二总线段还具有用于传播高频信号的至少一对传输线。第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个设备在大致相同的时间连接到第一总线段。而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间或控制，由信号携带。

9. 发明授权

US06687319B1 Spread spectrum clocking of digital signals 有权
标题翻译：扩频数字信号时钟
公开(公告)号：US06687319B1
公开(公告)日：2004-02-03
申请号：US09245140
申请日：1999-02-04
申请人： Donald V. Perino , Haw-Jyh Liaw
发明人： Donald V. Perino , Haw-Jyh Liaw
IPC分类号： H04L700
CPC分类号： H04B15/04 , H04B1/707 , H04B2201/70715 , H04B2215/064 , H04B2215/067
摘要： A clock signal desired to be transmitted to various components of the electronic system is combined with a noise signal to generate a spread spectrum clock signal which, in turn, is distributed with an associated reference signal to selected components of the system using two-channel communication links. A receiving circuit within each of the selected components recovers the original clock signal from the spread spectrum clock signal and its associated reference signal. In one embodiment, the clock signal is combined with the noise signal in an exclusive-OR logic gate to generate a spread spectrum clock signal which is distributed to receiving components using a first channel. The noise signal is transmitted as the reference signal using the second channel. The two channel signals are combined in an exclusive-OR gate of one or more receiving circuits to recover the clock signal. In other embodiments, transmission of the clock signal is alternated between the two channels in accordance with the logic state of the noise signal. Here, the two channel signals are combined in an OR logic gate of each receiving circuit to recover the clock signal.
摘要翻译：期望发送到电子系统的各种组件的时钟信号与噪声信号组合以产生扩展频谱时钟信号，该扩展频谱时钟信号又将相关参考信号分配给使用双声道通信的系统的选定组件链接。每个选定组件内的接收电路从扩频时钟信号及其相关参考信号中恢复原始时钟信号。在一个实施例中，时钟信号与异或逻辑门中的噪声信号组合以产生扩展频谱时钟信号，该扩频时钟信号使用第一通道分配给接收组件。使用第二通道将噪声信号作为参考信号发送。两个信道信号在一个或多个接收电路的异或门中组合以恢复时钟信号。在其他实施例中，时钟信号的传输根据噪声信号的逻辑状态在两个信道之间交替。这里，两个信道信号被组合在每个接收电路的或逻辑门中以恢复时钟信号。

10. 发明授权

US06266730B1 High-frequency bus system 失效
标题翻译：高频总线系统
公开(公告)号：US06266730B1
公开(公告)日：2001-07-24
申请号：US09507303
申请日：2000-02-18
申请人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
发明人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
IPC分类号： H05K102
CPC分类号： G11C5/063 , G06F13/1684 , G06F13/4086 , G06F13/409 , G06F13/4247 , G11C5/04 , G11C7/1048 , H05K1/023 , H05K1/0246 , H05K1/0248 , H05K1/14 , H05K7/1459 , H05K2201/044 , H05K2201/09263 , H05K2201/10022 , H05K2201/10159 , H05K2201/10689
摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.
摘要翻译：尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。高频总线系统还包括没有与其连接的设备的第二总线段。第二总线段还具有用于传播高频信号的至少一对传输线。第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个设备在大致相同的时间连接到第一总线段。而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间或控制，由信号携带。

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