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1. 发明授权

US08756395B2 Controlling DRAM at time DRAM ready to receive command when exiting power down 有权
标题翻译：在DRAM时刻控制DRAM，准备在断电时接收命令
公开(公告)号：US08756395B2
公开(公告)日：2014-06-17
申请号：US13406465
申请日：2012-02-27
申请人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
发明人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
IPC分类号： G06F13/00
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.
摘要翻译：在实施例中提供了存储器件和系统的操作方法。初始化操作在初始化序列期间以第一操作频率进行。然后在第二操作频率下执行存储器存取操作。第二个操作频率高于第一个操作频率。此外，存储器访问操作包括读取操作和写入操作。在实施例中，从串行存在检测装置读取表示第一操作频率和第二操作频率的信息。

2. 发明授权

US08320202B2 Clocked memory system with termination component 有权
标题翻译：带终端组件的定时存储系统
公开(公告)号：US08320202B2
公开(公告)日：2012-11-27
申请号：US11767983
申请日：2007-06-25
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C5/04 , G11C5/063 , G11C7/1048
摘要： A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to provide second data, associated with the write command, to the second memory device. A control signal path is coupled to the first and second memory devices and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component. A third signal line is provided to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first and second memory devices.
摘要翻译：一种具有第一和第二存储器件和终端部件的存储器系统。第一信号线耦合到第一存储器设备，以向第一存储器设备提供与写命令相关联的第一数据，以及耦合到第二存储器设备以提供与写命令相关联的第二数据的第二信号线，到第二存储设备。控制信号路径被耦合到第一和第二存储器件和终端部件，使得在到达终端部件之前，在控制信号路径上传播的写入命令传播通过第一存储器件和第二存储器件。提供第三信号线来传送时钟信号，该时钟信号指示在控制信号路径上传播的写入命令何时被第一和第二存储器件采样。

3. 发明授权

US08305839B2 Memory device having multiple power modes 有权
标题翻译：具有多种功率模式的存储器件
公开(公告)号：US08305839B2
公开(公告)日：2012-11-06
申请号：US13352177
申请日：2012-01-17
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
摘要翻译：描述了具有存储器核心的存储器件。存储器件包括时钟接收器电路，用于接收读取命令的第一接口，数据接口和用于接收功率模式信息的第二接口。数据接口与第一个接口分开。第二个接口与第一个接口和数据接口分开。存储器件具有多个功率模式，包括时钟接收器电路，第一接口和数据接口关闭的第一模式; 时钟接收器被接通并且第一接口和数据接口被关闭的第二模式; 以及其中时钟接收器和第一接口被接通的第三模式。在第三种模式下，当第一个接口接收到命令时，数据接口被打开，以响应命令输出数据。

4. 发明申请

US20120113738A1 Memory Device Having Multiple Power Modes 有权
公开(公告)号：US20120113738A1
公开(公告)日：2012-05-10
申请号：US13352177
申请日：2012-01-17
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampe , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampe , Donald C. Stark
IPC分类号： G11C5/14
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.

5. 发明申请

US20110248761A1 Phase Adjustment Apparatus and Method for a Memory Device Signaling System 有权
标题翻译：相位调整装置及存储器件信号系统的方法
公开(公告)号：US20110248761A1
公开(公告)日：2011-10-13
申请号：US13163618
申请日：2011-06-17
申请人： Craig E. Hampel , Richard E. Perego , Stefanos S. Sidiropoulos , Ely K. Tsern , Fredrick A. Ware
发明人： Craig E. Hampel , Richard E. Perego , Stefanos S. Sidiropoulos , Ely K. Tsern , Fredrick A. Ware
IPC分类号： H03K5/13
CPC分类号： G11C11/4076 , G06F3/061 , G06F3/0629 , G06F3/0671 , G06F12/0246 , G11C7/10 , G11C7/1051 , G11C7/106 , G11C7/1066 , G11C7/1078 , G11C7/1087 , G11C7/22 , G11C7/222 , G11C11/40611 , G11C11/4072 , G11C11/4078 , G11C11/4093 , G11C21/00 , G11C2207/2254 , H04L7/0025 , H04L7/0079 , H04L7/0091
摘要： Apparatus and methods are disclosed for adjusting phase of data signals to compensate for phase-offset variations between devices during normal operation. The phase of data signals are adjusted individually in each transmit data unit and receive data unit across multiple data slices with a common set of phase vector clock signals and a corresponding clock cycle count signal. The transmission of signal information between a first device (such as a memory controller) and a second device (such as a memory component) occurs without errors even when the accumulated delays between the first device and second device change by a half symbol time interval or more during operation of the system. The apparatus reduces the circuitry required, such as phase-lock-loops, for individually adjusting the phase of each transmit data unit and receive data unit across multiple data slices, which in turn results in reduction in complexity and cost of the system.
摘要翻译：公开了用于调整数据信号的相位以补偿正常操作期间设备之间的相位偏移变化的装置和方法。数据信号的相位在每个发送数据单元中单独调整，并且通过一组公共的相位矢量时钟信号和相应的时钟周期计数信号在多个数据切片之间接收数据单元。即使当第一设备和第二设备之间的累积延迟改变半符号时间间隔时，在第一设备（诸如存储器控制器）和第二设备（诸如存储器组件）之间的信号信息的传输也没有错误地发生，或者更多的是在系统的运行过程中。该装置减少了所需的电路，例如锁相环，用于单独调整每个发送数据单元的相位并在多个数据切片之间接收数据单元，这又导致系统的复杂性和成本的降低。

6. 发明申请

US20110119551A1 Memory System with Error Detection and Retry Modes of Operation 有权
标题翻译：具有错误检测和重试操作模式的内存系统
公开(公告)号：US20110119551A1
公开(公告)日：2011-05-19
申请号：US12940942
申请日：2010-11-05
申请人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
发明人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
IPC分类号： H04L1/18 , H03M13/15 , G06F11/10 , G06F11/14
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
摘要翻译：存储器系统包括具有至少一个信号线的链路和控制器。所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。至少一个接收器耦合到链路以接收第二数据。第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

7. 发明申请

US20110090755A1 Memory Device Having Multiple Power Modes 有权
标题翻译：具有多种功率模式的存储器件
公开(公告)号：US20110090755A1
公开(公告)日：2011-04-21
申请号：US12975322
申请日：2010-12-21
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a first interface to receive a read command, a data interface, and a second interface to receive power mode information. The data interface is separate from the first interface. The second interface is separate from the first interface and the data interface. The memory device has a plurality of power modes, including a first mode in which the clock receiver circuit, first interface, and data interface are turned off; a second mode in which the clock receiver is turned on and the first interface and data interface are turned off; and a third mode in which the clock receiver and first interface are turned on. In the third mode, the data interface is turned on when the first interface receives the command, to output data in response to the command.
摘要翻译：描述了具有存储器核心的存储器件。存储器件包括时钟接收器电路，用于接收读取命令的第一接口，数据接口和用于接收功率模式信息的第二接口。数据接口与第一个接口分开。第二个接口与第一个接口和数据接口分开。存储器件具有多个功率模式，包括时钟接收器电路，第一接口和数据接口关闭的第一模式; 时钟接收器被接通并且第一接口和数据接口被关闭的第二模式; 以及其中时钟接收器和第一接口被接通的第三模式。在第三种模式下，当第一个接口接收到命令时，数据接口被打开，以响应命令输出数据。

8. 发明申请

US20100061047A1 Upgradable Memory System with Reconfigurable Interconnect 有权
标题翻译：可重构互连的可升级内存系统
公开(公告)号：US20100061047A1
公开(公告)日：2010-03-11
申请号：US12538613
申请日：2009-08-10
申请人： Richard E. Perego , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E. Perego , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F1/16
CPC分类号： G06F13/409 , G11C5/04 , G11C2207/105 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14 , Y02D10/151
摘要： Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.
摘要翻译：描述的是采用可配置的片上终端元件的系统，其允许用户从两个或多个端接拓扑中进行选择。一个拓扑结构可编程，以支持轨到轨或半电源终端。另一种拓扑选择性地包括固定或可变滤波器元件，从而允许针对不同级别的速度性能和功耗来调整终端特性。终端电压和阻抗也可能会被调整。

9. 发明申请

US20100046314A1 Memory Device Having a Read Pipeline and a Delay Locked Loop 有权
标题翻译：具有读取流水线和延迟锁定环路的存储器件
公开(公告)号：US20100046314A1
公开(公告)日：2010-02-25
申请号：US12608209
申请日：2009-10-29
申请人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
发明人： Ely K. Tsern , Richard M. Barth , Craig E. Hampel , Donald C. Stark
IPC分类号： G11C8/18
CPC分类号： G11C7/22 , G06F1/3225 , G06F1/324 , G06F1/3275 , G06F9/3869 , G11C7/1039 , G11C7/1072 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D50/20
摘要： A memory device having a memory core is described. The memory device includes a clock receiver circuit, a control interface, a data interface, a delay locked loop circuit, a read pipeline circuit and a circuit to provide an internal clock signal. The clock receiver circuit receives an external clock signal. The control interface receives a command that specifies a read operation to the memory device. The data interface transfers data between the memory device and an external set of signal lines. The delay locked loop circuit, coupled to the clock receiver circuit, to generate the internal clock signal using the external clock signal. The read pipeline circuit provides read data accessed from the memory core to the data interface. The circuit provides the internal clock signal to the read pipeline circuit in response to receipt of the command that specifies the read operation.
摘要翻译：描述了具有存储器核心的存储器件。存储器件包括时钟接收器电路，控制接口，数据接口，延迟锁定环电路，读取流水线电路和用于提供内部时钟信号的电路。时钟接收器电路接收外部时钟信号。控制接口接收指定对存储器件的读取操作的命令。数据接口在存储器件和外部信号线组之间传送数据。延迟锁定环路电路，耦合到时钟接收器电路，以使用外部时钟信号产生内部时钟信号。读取管线电路将从存储器核心访问的读取数据提供给数据接口。响应于接收到指定读取操作的命令，该电路将内部时钟信号提供给读取管线电路。

10. 发明申请

US20090195497A1 GESTURE-BASED POWER MANAGEMENT OF A WEARABLE PORTABLE ELECTRONIC DEVICE WITH DISPLAY 有权
标题翻译：具有显示功能的易携带电子设备的基于功能的电源管理
公开(公告)号：US20090195497A1
公开(公告)日：2009-08-06
申请号：US12356457
申请日：2009-01-20
申请人： Alissa M. Fitzgerald , Ely K. Tsern , David J. Mooring , James A. Gasbarro
发明人： Alissa M. Fitzgerald , Ely K. Tsern , David J. Mooring , James A. Gasbarro
IPC分类号： G09G5/00 , G06F3/038 , G06F3/033
CPC分类号： G06F1/3203 , G06F1/3265 , G06F3/011 , G06F3/017 , G06F3/0346 , Y02D10/153
摘要： Methods and systems for providing gesture-based power management for a wearable portable electronic device with display are described. An inertial sensor is calibrated to a reference orientation relative to gravity. Motion of the portable device is tracked with respect to the reference orientation, and the display is enabled when the device is within a viewable range, wherein the viewable range is a predefined rotational angle range in each of x, y, and z axis, to a user based upon a position of the device with respect to the reference orientation. Furthermore, the display is turned off if an object is detected within a predetermined distance of the display for a predetermined amount of time.
摘要翻译：描述了用于为具有显示器的可穿戴便携式电子设备提供基于姿势的电源管理的方法和系统。惯性传感器被校准为相对于重力的参考方向。便携式设备的运动相对于参考方向被跟踪，并且当设备在可视范围内时显示被启用，其中可视范围是x，y和z轴中的每一个中的预定旋转角度范围，基于所述设备相对于所述参考方向的位置的用户。此外，如果在显示器的预定距离内检测到物体预定的时间量，则关闭显示。

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