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1. 再颁专利

USRE43720E1 Integrated circuit device having stacked dies and impedance balanced transmission lines 有权
标题翻译：具有堆叠管芯和阻抗平衡传输线的集成电路器件
公开(公告)号：USRE43720E1
公开(公告)日：2012-10-09
申请号：US11229445
申请日：2005-09-15
申请人： Donald V. Perino , Sayeh Khalili
发明人： Donald V. Perino , Sayeh Khalili
IPC分类号： H01L23/34 , H01L23/48 , H01L23/02 , H05K7/00
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/5385 , H01L24/48 , H01L24/49 , H01L24/50 , H01L25/0652 , H01L2224/0401 , H01L2224/05599 , H01L2224/32145 , H01L2224/4809 , H01L2224/48091 , H01L2224/48095 , H01L2224/48145 , H01L2224/48227 , H01L2224/484 , H01L2224/49175 , H01L2224/73265 , H01L2224/85399 , H01L2225/06506 , H01L2225/0651 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06562 , H01L2225/06575 , H01L2225/06582 , H01L2225/06586 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01029 , H01L2924/01083 , H01L2924/014 , H01L2924/14 , H01L2924/15173 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19104 , H01L2924/30107 , H01L2924/3011 , H01L2224/45099 , H01L2924/00012
摘要： A multi-chip device which includes a plurality of integrated circuit die disposed one over another. Each integrated circuit die includes one or a plurality of bond pads. One or a plurality of conductors are disposed to electrically couple the bond pads of vertically adjacent integrated circuit die. Each conductor is designed, calculated, specified and/or predetermined to have a length so as to behave as a segment in a multi-drop transmission line. The multi-drop transmission line may be terminated at one end or utilized in a flow-through approach. In one embodiment, an integrated circuit die may be horizontally offset with respect to a vertically adjacent integrated circuit die to expose the periphery region. In another embodiment, each integrated circuit die may be stacked and aligned in a vertical column. In this embodiment, a spacer such as a thermally conductive spacer is disposed between each integrated circuit die in the stack. In yet another embodiment, two or more stacks of integrated circuit die are disposed in the multi-chip device and the one or more multi-drop transmission lines may be implemented in the flow-through approach. The plurality of integrated circuit die may comprise a plurality of memory devices, or a plurality of memory devices and a controller, or a plurality of controllers and a plurality of memory devices.
摘要翻译：一种多芯片器件，包括多个集成电路管芯，所述多个集成电路管芯设置在另一个上。每个集成电路管芯包括一个或多个接合焊盘。设置一个或多个导体以电耦合垂直相邻的集成电路管芯的接合焊盘。每个导体被设计，计算，指定和/或预定为具有一个长度以便在多点传输线路中作为一个段。多滴传输线可以在一端终止或以流通方式使用。在一个实施例中，集成电路管芯可以相对于垂直相邻的集成电路管芯水平地偏移以暴露外围区域。在另一个实施例中，每个集成电路管芯可以堆叠并在垂直列中对准。在该实施例中，诸如导热间隔件之类的间隔件设置在堆叠中的每个集成电路管芯之间。在另一个实施例中，集成电路管芯的两个或多个堆叠设置在多芯片器件中，并且可以以流通方式实现一个或多个多点传输线。多个集成电路管芯可以包括多个存储器件，或多个存储器件和控制器，或多个控制器和多个存储器件。

2. 发明授权

US08096812B2 Chip socket assembly and chip file assembly for semiconductor chips 失效
标题翻译：用于半导体芯片的芯片插座组件和芯片文件组件
公开(公告)号：US08096812B2
公开(公告)日：2012-01-17
申请号：US11231640
申请日：2005-09-20
申请人： Donald V. Perino , Wayne S. Richardson , John B. Dillon
发明人： Donald V. Perino , Wayne S. Richardson , John B. Dillon
IPC分类号： H01R12/00 , H05K1/00
CPC分类号： H01R12/7005 , H01R12/7076 , H05K7/1431
摘要： The socket releasably couples a packaged integrated circuit to a circuit board. The socket includes a clamp, a latch, and an array interconnect. The clamp is configured to be pivotally coupled to a circuit board. The latch is configured to be coupled to the circuit board and configured to releasably hold the clamp in a predetermined position. The array interconnect configured to be coupled to the printed circuit board. In use the latch releasably holds the hinged clamp in the predetermined position to clamp both a packaged integrated circuit between the clamp and the array interconnect, and the array interconnect between the packaged integrated circuit and the circuit board.
摘要翻译：插座将封装的集成电路可释放地耦合到电路板。插座包括夹具，闩锁和阵列互连。夹具被构造成枢转地联接到电路板。闩锁构造成联接到电路板并且构造成将夹具可释放地保持在预定位置。阵列互连配置为耦合到印刷电路板。在使用中，闩锁将铰链夹具可释放地保持在预定位置，以夹紧夹具和阵列互连之间的封装集成电路，以及封装集成电路和电路板之间的阵列互连。

3. 发明授权

US07627043B2 Method and apparatus for transmitting data with reduced coupling noise 失效
标题翻译：用耦合噪声降低传输数据的方法和装置
公开(公告)号：US07627043B2
公开(公告)日：2009-12-01
申请号：US11130502
申请日：2005-05-17
申请人： Mark A. Horowitz , Donald V. Perino
发明人： Mark A. Horowitz , Donald V. Perino
IPC分类号： H04B3/00 , H04L25/00
CPC分类号： H04B3/32
摘要： A first integrated circuit is coupled to a first connector. A second connector is coupled to the first connector through multiple conductors, in which alternating pairs of conductors are reversed. A second integrated circuit is coupled to the second connector through a second group of conductors. The first integrated circuit includes multiple differential drivers and the second integrated circuit includes multiple differential receivers. The inductive coupling coefficient of the first device is modified to be substantially the same as the inductive coupling coefficient of the second device.
摘要翻译：第一集成电路耦合到第一连接器。第二连接器通过多个导体耦合到第一连接器，其中交替的导线对被反转。第二集成电路通过第二组导体耦合到第二连接器。第一集成电路包括多个差分驱动器，第二集成电路包括多个差动接收器。第一装置的电感耦合系数被修改为与第二装置的电感耦合系数基本相同。

4. 再颁专利

USRE39153E1 Connector with integral transmission line bus 有权
标题翻译：带集成传输线总线的连接器
公开(公告)号：USRE39153E1
公开(公告)日：2006-07-04
申请号：US09871313
申请日：2001-05-31
申请人： Donald V. Perino , James A. Gasbarro , Nancy David Dillon
发明人： John B. Dillon
IPC分类号： H01R9/00
CPC分类号： H01R12/7076 , H01R12/712 , H01R13/658
摘要： A socket (14) includes a first bus conductor (22a) having two or more contact regions (24) and a second bus conductor (22b) arranged substantially parallel to the first bus conductor and having two or more contact regions (24). The first and second bus conductors are spaced relative to one another so as to provide a predetermined electrical impedance and may be arranged to carry electrical signals as transmission lines. A dielectric spacer (36) may be disposed between the first and second bus conductors to provide the spacing. Contact regions (24) of the first and second conductors (22a, 22b) may provide compliant coupling regions for the socket (14). The contact regions (24) of the first bus conductor (22a) may be positioned within the socket (14) so as to contact a lead disposed on a first side of a circuit element (16) and the contact regions (24) of the second bus conductor (22b) may be positioned within the socket (14) so as to contact the lead disposed on the second side of the circuit element (16).
摘要翻译：插座（14）包括具有两个或多个接触区域（24）的第一总线导体（22a）和基本上平行于第一总线导体布置并具有两个或多个接触区域（24）的第二总线导体（22b）。第一和第二总线导体相对于彼此间隔开以提供预定的电阻抗，并且可以被布置为承载作为传输线的电信号。电介质间隔物（36）可以设置在第一和第二总线导体之间以提供间隔。第一和第二导体（22a，22b）的接触区域（24）可以为插座（14）提供顺应的耦合区域。第一总线导体（22a）的接触区域（24）可以定位在插座（14）内，以便接触设置在电路元件（16）的第一侧上的引线和接触区域（24）的接触区域第二总线导体（22b）可以定位在插座（14）内，以便接触设置在电路元件（16）的第二侧上的引线。

5. 发明授权

US06999332B2 Semiconductor package with a controlled impedance bus and method of forming same 失效
公开(公告)号：US06999332B2
公开(公告)日：2006-02-14
申请号：US10749214
申请日：2003-12-30
申请人： Nader Gamini , Donald V. Perino
发明人： Nader Gamini , Donald V. Perino
IPC分类号： G11C5/02
CPC分类号： H01L22/22 , H01L23/525 , H01L23/5382 , H01L23/66 , H01L24/48 , H01L24/49 , H01L2224/16 , H01L2224/48091 , H01L2224/4824 , H01L2224/49 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/14 , H01L2924/15311 , H01L2924/30107 , H01L2924/3011 , H01L2924/30111 , H05K1/141 , H05K1/185 , H05K3/368 , H05K2201/10159 , H05K2201/10522 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2224/0401
摘要： An apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.

6. 发明授权

US06687319B1 Spread spectrum clocking of digital signals 有权
标题翻译：扩频数字信号时钟
公开(公告)号：US06687319B1
公开(公告)日：2004-02-03
申请号：US09245140
申请日：1999-02-04
申请人： Donald V. Perino , Haw-Jyh Liaw
发明人： Donald V. Perino , Haw-Jyh Liaw
IPC分类号： H04L700
CPC分类号： H04B15/04 , H04B1/707 , H04B2201/70715 , H04B2215/064 , H04B2215/067
摘要： A clock signal desired to be transmitted to various components of the electronic system is combined with a noise signal to generate a spread spectrum clock signal which, in turn, is distributed with an associated reference signal to selected components of the system using two-channel communication links. A receiving circuit within each of the selected components recovers the original clock signal from the spread spectrum clock signal and its associated reference signal. In one embodiment, the clock signal is combined with the noise signal in an exclusive-OR logic gate to generate a spread spectrum clock signal which is distributed to receiving components using a first channel. The noise signal is transmitted as the reference signal using the second channel. The two channel signals are combined in an exclusive-OR gate of one or more receiving circuits to recover the clock signal. In other embodiments, transmission of the clock signal is alternated between the two channels in accordance with the logic state of the noise signal. Here, the two channel signals are combined in an OR logic gate of each receiving circuit to recover the clock signal.
摘要翻译：期望发送到电子系统的各种组件的时钟信号与噪声信号组合以产生扩展频谱时钟信号，该扩展频谱时钟信号又将相关参考信号分配给使用双声道通信的系统的选定组件链接。每个选定组件内的接收电路从扩频时钟信号及其相关参考信号中恢复原始时钟信号。在一个实施例中，时钟信号与异或逻辑门中的噪声信号组合以产生扩展频谱时钟信号，该扩频时钟信号使用第一通道分配给接收组件。使用第二通道将噪声信号作为参考信号发送。两个信道信号在一个或多个接收电路的异或门中组合以恢复时钟信号。在其他实施例中，时钟信号的传输根据噪声信号的逻辑状态在两个信道之间交替。这里，两个信道信号被组合在每个接收电路的或逻辑门中以恢复时钟信号。

7. 发明授权

US06657871B2 Multiple channel modules and bus systems using same 失效
标题翻译：多通道模块和使用相同的总线系统
公开(公告)号：US06657871B2
公开(公告)日：2003-12-02
申请号：US10177747
申请日：2002-06-20
申请人： Donald V. Perino , Belgacem Haba , Sayeh Khalili
发明人： Donald V. Perino , Belgacem Haba , Sayeh Khalili
IPC分类号： H05K710
CPC分类号： G11C5/04 , G06F13/409 , G11C5/00 , H05K1/023 , H05K1/117 , H05K1/141 , H05K1/147 , H05K1/148 , H05K7/1459 , H05K2201/10189
摘要： Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.
摘要翻译：公开了可用于实现具有1至N个信道的模块的各种模块结构。总线系统可以通过这种模块的互连形成。

8. 发明授权

US06657468B1 Apparatus and method for controlling edge rates of digital signals 失效
标题翻译：用于控制数字信号边沿速率的装置和方法
公开(公告)号：US06657468B1
公开(公告)日：2003-12-02
申请号：US09467446
申请日：1999-12-20
申请人： Scott C. Best , Donald V. Perino
发明人： Scott C. Best , Donald V. Perino
IPC分类号： H03K512
CPC分类号： H03K19/01721 , H03K19/01742
摘要： A circuit to control the edge rate of a digital signal includes a conductor to carry a digital signal. A first capacitive component has a first node and a second node, with the second node being coupled to the conductor. A first phase control circuit has a first input node coupled to the conductor, a second input node to receive a first enable signal and an output node coupled to the first node of the first capacitive component. The first phase control circuit processes the digital signal from the conductor and the first enable signal to produce a control signal at the output node to control the edge rate of the digital signal. The first phase control circuit produces the control signal in one of at least two different phase relationships with the digital signal according to a state of the first enable signal. The control signal may be in phase with the digital signal or complementary to the digital signal.
摘要翻译：用于控制数字信号的边沿速率的电路包括承载数字信号的导体。第一电容部件具有第一节点和第二节点，其中第二节点耦合到导体。第一相位控制电路具有耦合到导体的第一输入节点，接收第一使能信号的第二输入节点和耦合到第一电容部件的第一节点的输出节点。第一相位控制电路处理来自导体的数字信号和第一使能信号，以在输出节点产生控制信号，以控制数字信号的边沿速率。第一相位控制电路根据第一使能信号的状态，产生与数字信号的至少两个不同相位关系之一的控制信号。控制信号可以与数字信号同相或与数字信号互补。

9. 发明授权

US06266730B1 High-frequency bus system 失效
标题翻译：高频总线系统
公开(公告)号：US06266730B1
公开(公告)日：2001-07-24
申请号：US09507303
申请日：2000-02-18
申请人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
发明人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
IPC分类号： H05K102
CPC分类号： G11C5/063 , G06F13/1684 , G06F13/4086 , G06F13/409 , G06F13/4247 , G11C5/04 , G11C7/1048 , H05K1/023 , H05K1/0246 , H05K1/0248 , H05K1/14 , H05K7/1459 , H05K2201/044 , H05K2201/09263 , H05K2201/10022 , H05K2201/10159 , H05K2201/10689
摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.
摘要翻译：尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。高频总线系统还包括没有与其连接的设备的第二总线段。第二总线段还具有用于传播高频信号的至少一对传输线。第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个设备在大致相同的时间连接到第一总线段。而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间或控制，由信号携带。

10. 发明授权

US6002589A Integrated circuit package for coupling to a printed circuit board 失效
标题翻译：用于耦合到印刷电路板的集成电路封装
公开(公告)号：US6002589A
公开(公告)日：1999-12-14
申请号：US897784
申请日：1997-07-21
申请人： Donald V. Perino , John B. Dillon, deceased
发明人： Donald V. Perino , John B. Dillon, deceased
IPC分类号： H01L23/498 , H05K3/36 , H05K7/02 , H05K1/14 , H05K7/12 , H05K7/20
CPC分类号： H05K3/365 , H01L23/4985 , H01L2224/48091 , H01L2224/48227 , H01L2924/30107
摘要： A method and apparatus for an integrated circuit package is provided. The integrated circuit package is designed for coupling an integrated circuit to a printed circuit board. The integrated circuit package includes a base having a bottom and a side. A flex circuit having traces therein is coupled to the base. The traces in the flex circuit are designed to couple to the leads of the integrated circuit. The traces further are designed to couple to traces on the printed circuit board.
摘要翻译：提供了一种用于集成电路封装的方法和装置。集成电路封装设计用于将集成电路耦合到印刷电路板。集成电路封装包括具有底部和侧面的基座。其中具有痕迹的柔性电路耦合到基座。柔性电路中的迹线被设计成耦合到集成电路的引线。迹线进一步被设计成耦合到印刷电路板上的迹线。

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