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1. 发明授权

US07167039B2 Memory device having an adjustable voltage swing setting 有权
标题翻译：具有可调电压摆幅设置的存储器件
公开(公告)号：US07167039B2
公开(公告)日：2007-01-23
申请号：US10890972
申请日：2004-07-14
申请人： Billy Wayne Garrett, Jr. , Nancy David Dillon, legal representative , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： John B. Dillon, deceased
IPC分类号： G05F1/10
CPC分类号： H04L25/028 , G06F13/4077 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C29/02 , G11C29/021 , G11C29/028 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/0282 , H04L25/0298
摘要： A method of operating an integrated circuit including an output driver. The method includes storing a value in a register, wherein the value is representative of a voltage swing setting of an output driver. The voltage swing setting of the output driver is adjusted using a counter that holds a count value representing an update to the voltage swing setting. The count value is updated in accordance with a signal that indicates an adjustment to the voltage swing setting. In addition, an integrated circuit memory device comprising an output driver, a register and a counter is provided. The counter updates a count value in response to a signal that indicates a direction to adjust the count value.
摘要翻译：一种操作包括输出驱动器的集成电路的方法。该方法包括将值存储在寄存器中，其中该值表示输出驱动器的电压摆幅设置。输出驱动器的电压摆幅设置使用保持表示电压摆幅设置的更新的计数值的计数器进行调整。根据指示对电压摆幅设定的调整的信号来更新计数值。此外，提供了包括输出驱动器，寄存器和计数器的集成电路存储器件。计数器响应于指示调整计数值的方向的信号来更新计数值。

2. 发明授权

US06462591B2 Semiconductor memory device having a controlled output driver characteristic 失效
标题翻译：具有受控输出驱动器特性的半导体存储器件
公开(公告)号：US06462591B2
公开(公告)日：2002-10-08
申请号：US09882420
申请日：2001-06-14
申请人： Billy Wayne Garrett, Jr. , John B. Dillon , by Nancy David Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： Billy Wayne Garrett, Jr. , John B. Dillon , by Nancy David Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
IPC分类号： H03B100
CPC分类号： G11C7/1057 , G06F13/4077 , G11C7/1051 , G11C7/106 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/028 , H04L25/0282 , H04L25/0298
摘要： A semiconductor memory device including an array of memory cells. The memory device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. The memory device further includes a voltage divider coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. The memory device further includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.
摘要翻译：一种包括存储单元阵列的半导体存储器件。存储器件包括耦合到第一输出端的第一输出驱动器和耦合到第二输出端的第二输出驱动器。存储器件还包括耦合在第一和第二输出端子之间的分压器，以基于存在于第一输出端子上的电压电平和第二输出端子上存在的电压电平产生控制电压。存储器件还包括耦合到分压器的比较器，用于将控制电压与参考电压进行比较，其中基于控制电压和参考电压之间的比较来调节第一输出驱动器的电压摆幅量。

3. 发明授权

US06266730B1 High-frequency bus system 失效
标题翻译：高频总线系统
公开(公告)号：US06266730B1
公开(公告)日：2001-07-24
申请号：US09507303
申请日：2000-02-18
申请人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
发明人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
IPC分类号： H05K102
CPC分类号： G11C5/063 , G06F13/1684 , G06F13/4086 , G06F13/409 , G06F13/4247 , G11C5/04 , G11C7/1048 , H05K1/023 , H05K1/0246 , H05K1/0248 , H05K1/14 , H05K7/1459 , H05K2201/044 , H05K2201/09263 , H05K2201/10022 , H05K2201/10159 , H05K2201/10689
摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.
摘要翻译：尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。高频总线系统还包括没有与其连接的设备的第二总线段。第二总线段还具有用于传播高频信号的至少一对传输线。第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个设备在大致相同的时间连接到第一总线段。而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间或控制，由信号携带。

4. 发明授权

US5956284A Method and apparatus for writing to memory components 失效
公开(公告)号：US5956284A
公开(公告)日：1999-09-21
申请号：US167632
申请日：1998-10-06
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
IPC分类号： G11C7/10 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

5. 发明授权

US06870419B1 Memory system including a memory device having a controlled output driver characteristic 有权
标题翻译：存储器系统，包括具有受控输出驱动器特性的存储器件
公开(公告)号：US06870419B1
公开(公告)日：2005-03-22
申请号：US10625264
申请日：2003-07-23
申请人： Billy Wayne Garrett, Jr. , Nancy David Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： John B. Dillon
IPC分类号： G06F13/40 , G11C7/10 , H03K19/003 , H03K19/0185 , H04L25/02 , G05F1/10
CPC分类号： H04L25/028 , G06F13/4077 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C29/02 , G11C29/021 , G11C29/028 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/0282 , H04L25/0298
摘要： An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (125), a sampling latch (130), a current control counter (115), and a bitwise output driver (output driver A 107 and output driver B 111).
摘要翻译：使用输出驱动电路和电流控制技术，以便于低噪声的高速总线与高速动态RAM（DRAM）接口。该架构包括以下组件：输入隔离块（120），模拟分压器（104），输入比较器（125），采样锁存器（130），电流控制计数器（115）和按位输出驱动器（输出驱动器A107和输出驱动器B111）。

6. 发明授权

US06608507B2 Memory system including a memory device having a controlled output driver characteristic 失效
标题翻译：存储器系统，包括具有受控输出驱动器特性的存储器件
公开(公告)号：US06608507B2
公开(公告)日：2003-08-19
申请号：US10230931
申请日：2002-08-29
申请人： Billy Wayne Garrett, Jr. , John B. Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： Billy Wayne Garrett, Jr. , John B. Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
IPC分类号： H03B100
CPC分类号： G11C7/1057 , G06F13/4077 , G11C7/1051 , G11C7/106 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/028 , H04L25/0282 , H04L25/0298
摘要： A memory system and method of adjusting an output driver characteristic of a memory device that is included in the memory system. The method includes providing a command to the memory device that specifies a calibration mode and, during the calibration mode, driving a voltage level onto the first signal line using a first output driver. A first voltage level is derived from an amount of voltage swing generated by the first output driver driving the voltage level onto the first signal line. The method also includes: actively coupling a first comparator to the first signal line; when the first comparator is coupled to the first signal line, comparing the first voltage level with a reference voltage using the first comparator; and adjusting the amount of voltage swing to arrive at a calibrated voltage swing level. In addition, the method includes actively isolation the first comparator from the first signal line upon exiting the calibration mode. The memory device is operable in a normal read operation upon exiting the calibration mode. During the normal read operation, the first output driver is operable to output data onto the first signal line in accordance with the calibrated voltage swing level.
摘要翻译：一种存储系统和调整包含在存储器系统中的存储器件的输出驱动器特性的方法。该方法包括向存储器件提供指定校准模式的命令，并且在校准模式期间，使用第一输出驱动器将电压电平驱动到第一信号线上。第一电压电平是从驱动第一信号线上的电压电平的第一输出驱动器产生的电压摆幅的量导出的。该方法还包括：主动地将第一比较器耦合到第一信号线; 当所述第一比较器耦合到所述第一信号线时，使用所述第一比较器将所述第一电压电平与参考电压进行比较; 并且调整电压摆幅的量以达到校准的电压摆幅水平。此外，该方法包括在退出校准模式时将第一比较器与第一信号线主动隔离。存储器件在退出校准模式时可在正常读取操作中操作。在正常读取操作期间，第一输出驱动器可操作以根据校准的电压摆幅电平将数据输出到第一信号线上。

7. 发明授权

US06556052B2 Semiconductor controller device having a controlled output driver characteristic 有权
标题翻译：具有受控输出驱动器特性的半导体控制器装置
公开(公告)号：US06556052B2
公开(公告)日：2003-04-29
申请号：US09954561
申请日：2001-09-12
申请人： Billy Wayne Garrett, Jr. , John B. Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： Billy Wayne Garrett, Jr. , John B. Dillon , Michael Tak-Kei Ching , William F. Stonecypher , Andy Peng-Pui Chan , Matthew M. Griffin
IPC分类号： H03B100
CPC分类号： G11C7/1057 , G06F13/4077 , G11C7/1051 , G11C7/106 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/028 , H04L25/0282 , H04L25/0298
摘要： A semiconductor controller device to control the operation of a semiconductor memory device. The controller device includes a first output driver coupled to a first output terminal, and a second output driver coupled to a second output terminal. In addition, the controller device includes a voltage divider, coupled between the first and second output terminals, to generate a control voltage based on a voltage level present on the first output terminal and a voltage level present on the second output terminal. In addition, the controller device also includes a comparator, coupled to the voltage divider, to compare the control voltage with a reference voltage, wherein an amount of voltage swing of the first output driver is adjusted based on the comparison between the control voltage and the reference voltage.
摘要翻译：一种用于控制半导体存储器件的操作的半导体控制器装置。控制器装置包括耦合到第一输出端的第一输出驱动器和耦合到第二输出端的第二输出驱动器。此外，控制器装置包括耦合在第一和第二输出端子之间的分压器，以基于存在于第一输出端子上的电压电平和第二输出端子上存在的电压电平产生控制电压。此外，控制器装置还包括耦合到分压器的比较器，用于将控制电压与参考电压进行比较，其中基于控制电压和控制电压之间的比较来调节第一输出驱动器的电压摆幅量参考电压。

8. 发明授权

US06370668B1 High speed memory system capable of selectively operating in non-chip-kill and chip-kill modes 失效
标题翻译：高速存储器系统能够以非芯片杀死和芯片杀死模式选择性地运行
公开(公告)号：US06370668B1
公开(公告)日：2002-04-09
申请号：US09395160
申请日：1999-09-14
申请人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
发明人： Billy Wayne Garrett, Jr. , Frederick Abbott Ware , Craig E. Hampel , Richard M. Barth , Don Stark , Abhijit Mukund Abhyankar , Catherine Yuhjung Chen , Thomas J. Sheffler , Ely K. Tsern , Steven Cameron Woo
IPC分类号： G11C2900
CPC分类号： G06F11/1028 , G06F11/1044 , G11C7/1072
摘要： The present invention provides a high data bandwidth memory system capable of operating in non-chip-kill and chip-kill modes. In chip-kill mode, cycle multiplexing, bit multiplexing, and time and space multiplexing are used to read/write data and syndrome across a group of memory devices. Current command packet formats are adapted to communicate with the group of memory devices in chip-kill mode.
摘要翻译：本发明提供能够以非芯片杀死和芯片杀死模式操作的高数据带宽存储系统。在芯片杀死模式中，循环复用，位复用和时间和空间复用用于跨一组存储器件读/写数据和校正。当前命令分组格式适于以芯片杀死模式与该组存储器件进行通信。

9. 发明授权

US06975160B2 System including an integrated circuit memory device having an adjustable output voltage setting 失效
公开(公告)号：US06975160B2
公开(公告)日：2005-12-13
申请号：US11011077
申请日：2004-12-14
申请人： Billy Wayne Garrett, Jr. , Nancy David Dillon, legal representative , Michael Tak-Kei Ching , William E. Stonecynher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： John B. Dillon, deceased
IPC分类号： G06F13/40 , G11C7/10 , H03K19/003 , H03K19/0185 , H04L25/02 , G05F1/10
CPC分类号： H04L25/028 , G06F13/4077 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C29/02 , G11C29/021 , G11C29/028 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/0282 , H04L25/0298
摘要： A system including an integrated circuit memory device. The integrated circuit device comprises a register to store a value representative of an output voltage setting. A circuit holds a value representative of an adjustment to the output voltage setting. An output driver outputs a drive voltage during a calibration operation, wherein a signal is generated based on a comparison between a signal derived from the drive voltage and a reference voltage. The signal updates the value representative of the adjustment to the output voltage setting.

10. 发明授权

US06975159B2 Method of operation in a system having a memory device having an adjustable output voltage setting 失效
标题翻译：具有具有可调输出电压设置的存储器件的系统中的操作方法
公开(公告)号：US06975159B2
公开(公告)日：2005-12-13
申请号：US10981808
申请日：2004-11-05
申请人： Billy Wayne Garrett, Jr. , Nancy David Dillon, legal representative , Michael Tak-Kei Ching , William F. Stonecynher , Andy Peng-Pui Chan , Matthew M. Griffin
发明人： John B. Dillon, deceased
IPC分类号： G06F13/40 , G11C7/10 , H03K19/003 , H03K19/0185 , H04L25/02 , G05F1/10
CPC分类号： H04L25/028 , G06F13/4077 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C29/02 , G11C29/021 , G11C29/028 , H03K19/00384 , H03K19/018585 , H04L25/0266 , H04L25/0272 , H04L25/0282 , H04L25/0298
摘要： A method of operating a memory system that includes an integrated circuit memory device is provided. A value representing an output voltage setting of an output driver of the memory device is stored in a register. The output driver outputs the drive voltage. A signal derived from the drive voltage is compared to a reference signal to generate a signal that indicates an adjustment to the output voltage setting. The output voltage setting of the output driver is adjusted using a counter that holds a count value representing an update to the output voltage setting. The count value is updated in accordance with a signal that indicates the adjustment to the output voltage setting.
摘要翻译：提供了一种操作包括集成电路存储器件的存储器系统的方法。表示存储器件的输出驱动器的输出电压设置的值被存储在寄存器中。输出驱动器输出驱动电压。将从驱动电压导出的信号与参考信号进行比较，以产生指示对输出电压设置进行调整的信号。输出驱动器的输出电压设置使用一个计数器进行调整，该计数器保存表示输出电压设置更新的计数值。根据指示对输出电压设置的调整的信号来更新计数值。

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