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1. 发明授权

US06266730B1 High-frequency bus system 失效
标题翻译：高频总线系统
公开(公告)号：US06266730B1
公开(公告)日：2001-07-24
申请号：US09507303
申请日：2000-02-18
申请人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
发明人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
IPC分类号： H05K102
CPC分类号： G11C5/063 , G06F13/1684 , G06F13/4086 , G06F13/409 , G06F13/4247 , G11C5/04 , G11C7/1048 , H05K1/023 , H05K1/0246 , H05K1/0248 , H05K1/14 , H05K7/1459 , H05K2201/044 , H05K2201/09263 , H05K2201/10022 , H05K2201/10159 , H05K2201/10689
摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.
摘要翻译：尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。高频总线系统还包括没有与其连接的设备的第二总线段。第二总线段还具有用于传播高频信号的至少一对传输线。第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个设备在大致相同的时间连接到第一总线段。而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间或控制，由信号携带。

2. 发明授权

US6067594A High frequency bus system 失效
标题翻译：高频总线系统
公开(公告)号：US6067594A
公开(公告)日：2000-05-23
申请号：US938084
申请日：1997-09-26
申请人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
发明人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
IPC分类号： G06F13/00 , G06F13/40 , G11C5/00 , G11C5/06 , H05K1/02 , H05K1/14 , H05K7/14
CPC分类号： G11C5/063 , G06F13/1684 , G06F13/4086 , G06F13/409 , G06F13/4247 , G11C5/04 , H05K1/0246 , H05K1/0248 , H05K7/1459 , G11C7/1048 , H05K1/023 , H05K1/14 , H05K2201/044 , H05K2201/09263 , H05K2201/10022 , H05K2201/10159 , H05K2201/10689
摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.
摘要翻译：尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。高频总线系统还包括没有与其连接的设备的第二总线段。第二总线段还具有用于传播高频信号的至少一对传输线。第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个设备在大致相同的时间连接到第一总线段。而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间或控制，由信号携带。

3. 发明授权

US5680361A Method and apparatus for writing to memory components 失效
标题翻译：用于写入存储器组件的方法和装置
公开(公告)号：US5680361A
公开(公告)日：1997-10-21
申请号：US389561
申请日：1995-02-14
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
IPC分类号： G11C7/10 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： Additional modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.
摘要翻译：提供附加模式以增强存储器系统的功能和性能。在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。在另一个实施例中，提供单独的位掩码和字节掩码。字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。在计算机图形系统中，用于在前景和背景颜色之间进行选择。该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。

4. 发明授权

US5956284A Method and apparatus for writing to memory components 失效
公开(公告)号：US5956284A
公开(公告)日：1999-09-21
申请号：US167632
申请日：1998-10-06
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
IPC分类号： G11C7/10 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

5. 发明授权

US5940340A Method and apparatus for writing to memory components 失效
标题翻译：用于写入存储器组件的方法和装置
公开(公告)号：US5940340A
公开(公告)日：1999-08-17
申请号：US858068
申请日：1997-05-16
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
IPC分类号： G11C7/10 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.
摘要翻译：提供额外的操作模式以增强存储器系统的功能和性能。在一个实施例中，向每个列访问中使用的写入数据提供唯一的位掩码。在替代实施例中，提供位掩码寄存器和字节掩码寄存器以支持位电平和字节电平掩蔽。位掩码和写数据寄存器被实现为单个寄存器，以提供功能，同时最小化组件空间和成本。在另一个实施例中，提供单独的位掩码和字节掩码。字节掩码在一个周期内加载掩码数据，并在下一个“q”列写入访问期间使用。该结构提供无位掩蔽的操作模式，每行访问提供位掩码，并提供每列访问的位掩码。为了增强诸如二维图形系统的系统的功能，在替代实施例中，存储器系统具有两个寄存器和选择控制线，以从两个寄存器之一中选择数据。在计算机图形系统中，用于在前景和背景颜色之间进行选择。该实施例可以与所描述的其他实施例一起使用以提供增强的功能和性能。

6. 发明授权

US5844855A Method and apparatus for writing to memory components 失效
公开(公告)号：US5844855A
公开(公告)日：1998-12-01
申请号：US858014
申请日：1997-05-16
申请人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
发明人： Frederick A. Ware , John B. Dillon , Richard M. Barth , Billy Wayne Garrett, Jr. , John Girdner Atwood, Jr. , Michael P. Farmwald , Richard DeWitt Crisp
IPC分类号： G11C7/10 , G11C11/401
CPC分类号： G11C7/109 , G11C7/1006 , G11C7/103 , G11C7/1045 , G11C7/1078 , G11C7/1087
摘要： Additional operating modes are provided to enhance the functionality and performance of a memory system. In one embodiment, a unique bit mask is supplied with the write data used in each column access. In an alternate embodiment, a bit mask register and byte mask register are provided to support bit level and byte level masking. The bit mask and write data registers are realized as a single register to provide the functionality while minimizing component space and cost. In another embodiment, a separate bit mask and byte mask are provided. The byte mask is loaded with mask data in one cycle and is used during the next "q" column write accesses. This structure provides for operating modes with no bit masking, with bit masks supplied for every row access, and with bit masks supplied with every column access. In order to enhance the functionality of a system, such as a two-dimensional graphics system, in an alternate embodiment, the memory system is provided with two registers and a select control line to select data from one of two registers. In a computer graphics system, this is used to select between foreground and background colors. The embodiment can be utilized in conjunction with the other embodiments described to provide enhanced functionality and performance.

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