专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120222037A1 DYNAMIC REPROVISIONING OF RESOURCES TO SOFTWARE OFFERINGS 审中-公开
标题翻译：动态修改资源给软件提供商
公开(公告)号：US20120222037A1
公开(公告)日：2012-08-30
申请号：US13034475
申请日：2011-02-24
申请人： Jerome Labat , Ramachandran Varadharajan , Sivakumar Prakash Thivakaram , Srinivas Nimmagadda
发明人： Jerome Labat , Ramachandran Varadharajan , Sivakumar Prakash Thivakaram , Srinivas Nimmagadda
IPC分类号： G06F9/46
CPC分类号： G06F9/5072
摘要： The disclosed embodiments provide a system that facilitates the maintenance and execution of a software offering. During operation, the system obtains a policy change associated with a service definition of the software offering. Next, the system updates one or more requirements associated with the software offering based on the policy change. Finally, the system uses the updated requirements to dynamically reprovision one or more resources for use by the software offering during execution of the software offering.
摘要翻译：所公开的实施例提供了便于维护和执行软件产品的系统。在操作期间，系统获得与软件产品的服务定义相关联的策略变化。接下来，系统基于策略更改来更新与软件提供相关联的一个或多个需求。最后，系统使用更新的要求来动态地重新配置一个或多个资源，供软件产品在软件产品执行期间使用。

2. 发明授权

US5663661A Modular bus with single or double parallel termination 失效
标题翻译：具有单或双并联终端的模块总线
公开(公告)号：US5663661A
公开(公告)日：1997-09-02
申请号：US680589
申请日：1996-07-12
申请人： John B. Dillon , Srinivas Nimmagadda , Alfredo Moncayo
发明人： John B. Dillon , Srinivas Nimmagadda , Alfredo Moncayo
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G06F13/40 , H03K17/16 , H03K19/003
CPC分类号： G06F13/4077 , H04L25/0298
摘要： A modular bus permitting single or double termination is described. The bus includes a terminated motherboard data net for communicating data signals between a master and one or more motherboard devices. A socket is used for coupling the data signals between the motherboard data net and a terminated module data net of a removable module. The module data net communicates the data signals between the master and one or more module devices. The data signal swing and level of reflection of the data signals are substantially independent of the presence of the module.
摘要翻译：描述了允许单端或双端接的模块总线。总线包括用于在主机和一个或多个主板设备之间传送数据信号的终止主板数据网。插座用于耦合主板数据网与可移除模块的端接模块数据网之间的数据信号。模块数据网在主机和一个或多个模块设备之间传送数据信号。数据信号摆幅和数据信号的反射水平基本上与模块的存在无关。

3. 发明授权

US07263149B2 Apparatus and method for generating a distributed clock signal 有权
标题翻译：用于产生分布式时钟信号的装置和方法
公开(公告)号：US07263149B2
公开(公告)日：2007-08-28
申请号：US10985490
申请日：2004-11-10
申请人： Frederick A. Ware , Kevin S. Donnelly , Ely K. Tsern , Srinivas Nimmagadda
发明人： Frederick A. Ware , Kevin S. Donnelly , Ely K. Tsern , Srinivas Nimmagadda
IPC分类号： H04L7/00
CPC分类号： G06F13/4243 , G06F1/12 , G06F5/06 , G06F7/68
摘要： The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a different integer number of clock cycles in a common period. Also, in addition to a gear ratio relationship, the clocks may have a synchronized edge at the end of the common period. For each clock, the cycles in the common period are “colored”, i.e., identified by a number (1st, 2nd, etc.). By using the coloring technique, the appropriate clock edge to perform a data or control signal transfer can be identified. The edges are preferably chosen to minimize the latency of the transfer.
摘要翻译：本发明提供一种在时钟域具有传动比关系的两个时钟域之间同步信号传输的方法和装置。齿轮比意味着时钟通过比例相关联，使得每个时钟在公共周期中具有不同的整数个时钟周期。此外，除了齿轮比关系之外，时钟可以在公共周期结束时具有同步边缘。对于每个时钟，公共周期中的周期是“着色的”，即由数字（第1，第2等）标识。通过使用着色技术，可以识别执行数据或控制信号传送的适当时钟边缘。优选地选择边缘以最小化转移的等待时间。

4. 发明申请

US20050063502A1 Apparatus and method for generating a distributed clock signal 有权
标题翻译：用于产生分布式时钟信号的装置和方法
公开(公告)号：US20050063502A1
公开(公告)日：2005-03-24
申请号：US10985490
申请日：2004-11-10
申请人： Frederick Ware , Kevin Donnelly , Ely Tsern , Srinivas Nimmagadda
发明人： Frederick Ware , Kevin Donnelly , Ely Tsern , Srinivas Nimmagadda
IPC分类号： G06F1/12 , G06F5/06 , G06F7/68 , G06F13/42 , H04L7/00
CPC分类号： G06F13/4243 , G06F1/12 , G06F5/06 , G06F7/68
摘要： The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a different integer number of clock cycles in a common period. Also, in addition to a gear ratio relationship, the clocks may have a synchronized edge at the end of the common period. For each clock, the cycles in the common period are “colored”, i.e., identified by a number (1st, 2nd, etc.). By using the coloring technique, the appropriate clock edge to perform a data or control signal transfer can be identified. The edges are preferably chosen to minimize the latency of the transfer.
摘要翻译：本发明提供一种在时钟域具有传动比关系的两个时钟域之间同步信号传输的方法和装置。齿轮比意味着时钟通过比例相关联，使得每个时钟在公共周期中具有不同的整数个时钟周期。此外，除了齿轮比关系之外，时钟可以在公共周期结束时具有同步边缘。对于每个时钟，公共周期中的周期是“着色的”，即由数字（第1，第2等）标识。通过使用着色技术，可以识别执行数据或控制信号传送的适当时钟边缘。优选地选择边缘以最小化转移的等待时间。

5. 发明授权

US6067594A High frequency bus system 失效
标题翻译：高频总线系统
公开(公告)号：US6067594A
公开(公告)日：2000-05-23
申请号：US938084
申请日：1997-09-26
申请人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
发明人： Donald V. Perino , Billy Wayne Garrett, Jr. , Haw-Jyh Liaw , David Nguyen , Srinivas Nimmagadda , James A. Gasbarro , Richard DeWitt Crisp
IPC分类号： G06F13/00 , G06F13/40 , G11C5/00 , G11C5/06 , H05K1/02 , H05K1/14 , H05K7/14
CPC分类号： G11C5/063 , G06F13/1684 , G06F13/4086 , G06F13/409 , G06F13/4247 , G11C5/04 , H05K1/0246 , H05K1/0248 , H05K7/1459 , G11C7/1048 , H05K1/023 , H05K1/14 , H05K2201/044 , H05K2201/09263 , H05K2201/10022 , H05K2201/10159 , H05K2201/10689
摘要： A high frequency bus system which insures uniform arrival times of high-fidelity signals to the devices on the high frequency bus, despite the use of the bus on modules and connectors. A high frequency bus system includes a first bus segment having one or more devices connected between a first and a second end. The first bus segment has at least a pair of transmission lines for propagating high frequency signals and the devices are coupled to the pair of transmission lines. The high frequency bus system also includes a second bus segment which has no devices connected to it. The second bus segment also has at least a pair of transmission lines for propagating high frequency signals. The first end of the first segment and second end of the second segment are coupled in series to form a chain of segments and when two signals are introduced to the first end of the second bus segment at the substantially the same time, they arrive at each device connected to the first bus segment at substantially the same time. Also, when two signals originate at a device connected to the first bus segment at substantially the same time, they arrive at the first end of the second bus segment at substantially the same time. Uniform arrival times hold despite the use of connectors to couple the segments together, despite the segments being located on modules, without the need for stubs, despite the presence of routing turns in the segments and despite the type of information, such as address, data or control, carried by the signals.
摘要翻译：尽管在模块和连接器上使用了总线，但高频总线系统确保高保真信号的均匀到达时间到高频总线上的设备。高频总线系统包括具有连接在第一和第二端之间的一个或多个设备的第一总线段。第一总线段具有用于传播高频信号的至少一对传输线，并且该装置耦合到该对传输线。高频总线系统还包括没有与其连接的设备的第二总线段。第二总线段还具有用于传播高频信号的至少一对传输线。第二段的第一段和第二端的第一端被串联耦合以形成链段，并且当两个信号在基本相同的时间被引入第二总线段的第一端时，它们到达每一个设备在大致相同的时间连接到第一总线段。而且，当两个信号在基本相同的时间起始于连接到第一总线段的设备时，它们在几乎相同的时间到达第二总线段的第一端。尽管使用连接器将段连接在一起，尽管分段位于模块上，而不需要存根，尽管存在分段中的路由选择，并且尽管信息类型（例如地址，数据）也是均匀到达时间或控制，由信号携带。

6. 发明授权

US5578940A Modular bus with single or double parallel termination 失效
标题翻译：具有单或双并联终端的模块总线
公开(公告)号：US5578940A
公开(公告)日：1996-11-26
申请号：US416326
申请日：1995-04-04
申请人： John B. Dillon , Srinivas Nimmagadda , Alfredo Moncayo
发明人： John B. Dillon , Srinivas Nimmagadda , Alfredo Moncayo
IPC分类号： G06F3/00 , G06F12/00 , G06F13/16 , G06F13/40 , H03K17/16 , H03K19/003
CPC分类号： G06F13/4077 , H04L25/0298
摘要： A modular bus permitting single or double termination is described. The bus includes a terminated motherboard data net for communicating data signals between a master and one or more motherboard devices. A socket is used for coupling the data signals between the motherboard data net and a terminated module data net of a removable module. The module data net communicates the data signals between the master and one or more module devices. The data signal swing and level of reflection of the data signals are substantially independent of the presence of the module.
摘要翻译：描述了允许单端或双端接的模块总线。总线包括用于在主机和一个或多个主板设备之间传送数据信号的终止的主板数据网。插座用于耦合主板数据网与可移除模块的端接模块数据网之间的数据信号。模块数据网在主机和一个或多个模块设备之间传送数据信号。数据信号摆动和数据信号的反射水平基本上与模块的存在无关。

7. 发明授权

US09483258B1 Multi-site provisioning of resources to software offerings using infrastructure slices 有权
标题翻译：使用基础设施片段将资源多站点配置到软件产品
公开(公告)号：US09483258B1
公开(公告)日：2016-11-01
申请号：US13095621
申请日：2011-04-27
申请人： Jerome Labat , Ramachandran Varadharajan , Joseph W. Armstrong , Srinivas Nimmagadda
发明人： Jerome Labat , Ramachandran Varadharajan , Joseph W. Armstrong , Srinivas Nimmagadda
IPC分类号： G06F9/44 , G06F9/445
CPC分类号： G06F8/71 , G06F8/60 , G06F8/61 , G06F8/65 , G06F9/505 , G06F9/5077 , G06F11/07
摘要： The disclosed embodiments provide a system that facilitates the deployment and execution of a software offering. During operation, the system obtains a set of requirements associated with a service definition of the software offering. Next, the system uses the requirements to automatically provision a set of infrastructure slices for use by the software offering without requiring manual configuration of the resources by a user, wherein each of the infrastructure slices includes a set of resources configured to support a workload associated with the software offering.
摘要翻译：所公开的实施例提供了有助于部署和执行软件产品的系统。在操作期间，系统获得与软件产品的服务定义相关联的一组要求。接下来，系统使用这些要求来自动地提供一组基础设施切片供软件提供使用，而不需要用户手动配置资源，其中每个基础设施切片都包括一组资源，其被配置为支持与软件产品。

8. 发明授权

US06836521B2 Apparatus and method for generating a distributed clock signal using gear ratio techniques 失效
标题翻译：使用齿轮比技术生成分布式时钟信号的装置和方法
公开(公告)号：US06836521B2
公开(公告)日：2004-12-28
申请号：US10091979
申请日：2002-03-04
申请人： Frederick A. Ware , Kevin S. Donnelly , Ely K. Tsern , Srinivas Nimmagadda
发明人： Frederick A. Ware , Kevin S. Donnelly , Ely K. Tsern , Srinivas Nimmagadda
IPC分类号： A04L700
CPC分类号： G06F13/4243 , G06F1/12 , G06F5/06 , G06F7/68
摘要： The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a different integer number of clock cycles in a common period. Also, in addition to a gear ratio relationship, the clocks may have a synchronized edge at the end of the common period. For each clock, the cycles in the common period are “colored”, i.e., identified by a number (1st, 2nd, etc.). By using the coloring technique, the appropriate clock edge to perform a data or control signal transfer can be identified. The edges are preferably chosen to minimize the latency of the transfer.
摘要翻译：本发明提供一种在时钟域具有传动比关系的两个时钟域之间同步信号传输的方法和装置。齿轮比意味着时钟通过比例相关联，使得每个时钟在公共周期中具有不同的整数个时钟周期。此外，除了齿轮比关系之外，时钟可以在公共周期结束时具有同步边缘。对于每个时钟，公共周期中的周期是“着色的”，即由数字（第1，第2等）标识。通过使用着色技术，可以识别执行数据或控制信号传送的适当时钟边缘。优选地选择边缘以最小化转移的等待时间。

9. 发明申请

US20090222280A1 System and method for certification data management 审中-公开
标题翻译：认证数据管理系统和方法
公开(公告)号：US20090222280A1
公开(公告)日：2009-09-03
申请号：US12073131
申请日：2008-02-29
申请人： Shiva Mittal , Srinivas Nimmagadda , Keith Robert Glascock , Shelly Renee Frazier , Bradley Todd Ford
发明人： Shiva Mittal , Srinivas Nimmagadda , Keith Robert Glascock , Shelly Renee Frazier , Bradley Todd Ford
IPC分类号： G06Q10/00
CPC分类号： G06Q10/00 , G06Q30/018 , Y02P90/845
摘要： A system and method are disclosed that provide for processing certification data. The system and method include determining a rating definition associated with an engine configuration, and associating an arrangement number with the rating definition. In addition, the system and method include associating a certification type with the arrangement number, and associating a certification dataset, created by recording emissions test results of one or more emissions data parameters, with the rating definition to generate a certification family. The one or more emissions data parameters are included in at least one of an emissions law or an emissions regulation.
摘要翻译：公开了提供处理认证数据的系统和方法。该系统和方法包括确定与发动机配置相关联的评级定义，以及将排列编号与评级定义相关联。此外，系统和方法包括将认证类型与安排编号相关联，并且将通过记录一个或多个排放数据参数的排放测试结果而创建的认证数据集与评级定义相关联，以生成认证系列。一个或多个排放数据参数包括在排放法或排放法规中的至少一个中。

10. 发明授权

US06396887B1 Apparatus and method for generating a distributed clock signal using gear ratio techniques 有权
标题翻译：使用齿轮比技术生成分布式时钟信号的装置和方法
公开(公告)号：US06396887B1
公开(公告)日：2002-05-28
申请号：US09169589
申请日：1998-10-09
申请人： Frederick A. Ware , Kevin S. Donnelly , Ely K. Tsern , Srinivas Nimmagadda
发明人： Frederick A. Ware , Kevin S. Donnelly , Ely K. Tsern , Srinivas Nimmagadda
IPC分类号： H04L700
CPC分类号： G06F13/4243 , G06F1/12 , G06F5/06 , G06F7/68
摘要： The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a different integer number of clock cycles in a common period. Also, in addition to a gear ratio relationship, the clocks may have a synchronized edge at the end of the common period. For each clock, the cycles in the common period are “colored”, i.e., identified by a number (1st, 2nd, etc.). By using the coloring technique, the appropriate clock edge to perform a data or control signal transfer can be identified. The edges are preferably chosen to minimize the latency of the transfer.
摘要翻译：本发明提供一种在时钟域具有传动比关系的两个时钟域之间同步信号传输的方法和装置。齿轮比意味着时钟通过比例相关联，使得每个时钟在公共周期中具有不同的整数个时钟周期。此外，除了齿轮比关系之外，时钟可以在公共周期结束时具有同步边缘。对于每个时钟，公共周期中的周期是“着色的”，即由数字（第1，第2等）标识。通过使用着色技术，可以识别执行数据或控制信号传送的适当时钟边缘。优选地选择边缘以最小化转移的等待时间。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式