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1. 发明授权

US06798024B1 BiCMOS process with low temperature coefficient resistor (TCRL) 失效
标题翻译： BiCMOS工艺与低温系数电阻（TCRL）
公开(公告)号：US06798024B1
公开(公告)日：2004-09-28
申请号：US09607080
申请日：2000-06-29
申请人： Donald Hemmenway , Jose Delgado , John Butler , Anthony Rivoli , Michael D. Church , George V. Rouse , Lawrence G. Pearce , George S. Bajor
发明人： Donald Hemmenway , Jose Delgado , John Butler , Anthony Rivoli , Michael D. Church , George V. Rouse , Lawrence G. Pearce , George S. Bajor
IPC分类号： H01L2976
CPC分类号： H01L28/20 , H01L21/763 , H01L21/8249 , H01L27/0635
摘要： A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient. A process for fabrication of the resistor is used which combines separate spacer oxide depositions, provides buried layers having different diffusion coefficients, incorporates dual dielectric trench sidewalls that double as a polish stop, supplies a spacer structure that controls precisely the emitter-base dimension, and integrates bipolar and CMOS devices with negligible compromise to the features of either type.
摘要翻译：低温度系数电阻（TCRL）具有一些未修复的离子注入损伤。损坏部分提高电阻并使电阻器对工作温度波动较不敏感多晶硅薄膜低温度系数电阻器和电阻器制造方法克服了现有技术的电阻问题系数，同时消除了步骤 BiCMOS制造工艺，优化双极设计权衡，改善无源器件隔离。在绝缘层（通常为二氧化硅或氮化硅）上形成电阻电阻器（TCRL）的低温度系数，该层包含具有相对高浓度的一种或多种物质的掺杂剂的多晶硅。对于注入电阻器而言，使用退火工艺，其比典型的现有技术的注入电阻器的退火工艺短，从而在电阻器中留下一些有意的未退火损坏。计划的损坏使TCRL具有更高的阻力，而不增加其温度系数。使用制造电阻器的方法，其组合分开的间隔氧化物沉积，提供具有不同扩散系数的掩埋层，并入双重介质沟槽侧壁作为抛光停止点，提供精确控制发射极基底尺寸的间隔结构，以及将双极和CMOS器件集成到任何一种类型的特性上都可忽略不计。

2. 发明授权

US06812108B2 BICMOS process with low temperature coefficient resistor (TCRL) 失效
标题翻译： BICMOS工艺采用低温系数电阻（TCRL）
公开(公告)号：US06812108B2
公开(公告)日：2004-11-02
申请号：US10393181
申请日：2003-03-19
申请人： Donald Hemmenway , Jose Delgado , John Butler , Anthony Rivoli , Michael D. Church , George V. Rouse , Lawrence G. Pearce , George Bajor
发明人： Donald Hemmenway , Jose Delgado , John Butler , Anthony Rivoli , Michael D. Church , George V. Rouse , Lawrence G. Pearce , George Bajor
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01L21/763 , H01L21/8249 , H01L27/0635
摘要： A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient. A process for fabrication of the resistor is used which combines separate spacer oxide depositions, provides buried layers having different diffusion coefficients, incorporates dual dielectric trench sidewalls that double as a polish stop, supplies a spacer structure that controls precisely the emitter-base dimension, and integrates bipolar and CMOS devices with negligible compromise to the features of either type.
摘要翻译：低温度系数电阻（TCRL）具有一些未修复的离子注入损伤。损坏部分会提高电阻，使电阻对工作温度波动较不敏感。多晶硅薄膜低温系数电阻器和电阻器制造方法克服了现有技术的电阻系数问题，同时消除了BiCMOS制造工艺的步骤，优化了双极设计的权衡，改善了无源器件隔离。在绝缘层（通常为二氧化硅或氮化硅）上形成电阻电阻器（TCRL）的低温度系数，该层包含具有相对高浓度的一种或多种物质的掺杂剂的多晶硅。对于注入电阻器而言，使用退火工艺，其比典型的现有技术的注入电阻器的退火工艺短，从而在电阻器中留下一些有意的未退火损坏。计划的损坏使TCRL具有更高的阻力，而不增加其温度系数。使用制造电阻器的方法，其组合分开的间隔氧化物沉积，提供具有不同扩散系数的掩埋层，并入双重介质沟槽侧壁作为抛光停止点，提供精确控制发射极基底尺寸的间隔结构，以及将双极和CMOS器件集成到任何一种类型的特性上都可忽略不计。

3. 发明授权

US06825532B2 Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone 失效
公开(公告)号：US06825532B2
公开(公告)日：2004-11-30
申请号：US09846795
申请日：2001-05-01
申请人： Jack H. Linn , William H. Speece , Michael G. Shlepr , George V. Rouse
发明人： Jack H. Linn , William H. Speece , Michael G. Shlepr , George V. Rouse
IPC分类号： H01L2701
CPC分类号： H01L21/3226 , H01L21/2007 , H01L21/76251 , Y10S438/977
摘要： A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.

4. 发明授权

US06246090B1 Power trench transistor device source region formation using silicon spacer 有权
公开(公告)号：US06246090B1
公开(公告)日：2001-06-12
申请号：US09525182
申请日：2000-03-14
申请人： Linda S. Brush , Jun Zeng , John J. Hackenberg , Jack H. Linn , George V. Rouse
发明人： Linda S. Brush , Jun Zeng , John J. Hackenberg , Jack H. Linn , George V. Rouse
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66378 , H01L29/66545 , H01L29/7397 , H01L29/749 , H01L29/7813
摘要： A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.

5. 发明授权

US5932022A SC-2 based pre-thermal treatment wafer cleaning process 失效
标题翻译：基于SC-2的预热处理晶片清洗工艺
公开(公告)号：US5932022A
公开(公告)日：1999-08-03
申请号：US64029
申请日：1998-04-21
申请人： Jack H. Linn , George V. Rouse , Sana Rafie , Roberta R. Nolan-Lobmeyer , Diana Lynn Hackenberg , Steven T. Slasor , Timothy A. Valade
发明人： Jack H. Linn , George V. Rouse , Sana Rafie , Roberta R. Nolan-Lobmeyer , Diana Lynn Hackenberg , Steven T. Slasor , Timothy A. Valade
IPC分类号： H01L21/304 , H01L21/306 , H01L21/316 , B08B3/12 , C23G1/02 , H01L21/02
CPC分类号： H01L21/02052 , H01L21/02238 , H01L21/02307 , H01L21/31662
摘要： Pre heat-treatment processing of a silicon wafer to grow a hydrophilic oxide layer includes an initial step of contacting the wafer with a pre-clean SC-1 bath, thereby producing a silicon wafer surface that is highly particle free. After a deionized water rinse, the wafer is scoured with an aqueous solution containing hydrofluoric acid and hydrochloric acid to remove metallic-containing oxide from the wafer surface. In order to grow a hydrophilic oxide layer, an SC-2 bath (containing hydrogen peroxide and a dilute concentration of metal-scouring HCl) is used. The resulting hydrophilic silicon oxide layer grown on the surface of the silicon wafer using the combined SC-1.fwdarw.HF/HCL.fwdarw.SC-2 wafer cleaning process has a metal concentration no greater than 1.times.10.sup.9. The diffusion length of minority carriers is increased from a range on the order of 500-600 microns to a range on the order of 800-900 microns.
摘要翻译：硅晶片的预热处理处理以生长亲水氧化物层包括使晶片与预清洁SC-1浴接触的初始步骤，从而产生高度无颗粒的硅晶片表面。去离子水冲洗后，用含有氢氟酸和盐酸的水溶液洗涤晶片，以从晶片表面去除含金属的氧化物。为了生长亲水氧化物层，使用SC-2浴（含有过氧化氢和稀释浓度的金属洗涤HCl）。使用组合的SC-1-> HF / HCL-> SC-2晶片清洁工艺在硅晶片的表面上生长的所得亲水性氧化硅层的金属浓度不大于1×109。少数载体的扩散长度从500-600微米的范围增加到约800-900微米的范围。

6. 发明授权

US5744852A Bonded wafer 失效
标题翻译：粘合晶片
公开(公告)号：US5744852A
公开(公告)日：1998-04-28
申请号：US710694
申请日：1996-09-19
申请人： Jack H. Linn , George Bajor , George V. Rouse
发明人： Jack H. Linn , George Bajor , George V. Rouse
IPC分类号： H01L21/20 , H01L29/06
CPC分类号： H01L21/2007 , Y10S148/012 , Y10S438/974
摘要： A bonded wafer with a bond junction having low resistivity due to the low level of oxides at the bond junction. A plasma that removes native oxide layers from wafers is exposed to the wafers. The plasma forms a hydrophobic polymer seal on the wafers, inhibiting subsequent native oxide growth upon exposure to air. The polymer seal on the wafers to be bonded are pressed together and the wafers are annealed to form the bonded wafer in a non-oxidizing ambient. The bond junction formed is primarily silicon to silicon and silicon to carbon bonds.
摘要翻译：具有键合结的键合晶片由于在键合结处的氧化物水平低而具有低电阻率。从晶片去除原生氧化物层的等离子体暴露于晶片。等离子体在晶片上形成疏水聚合物密封，在暴露于空气中时抑制随后的天然氧化物生长。将要接合的晶片上的聚合物密封件压在一起，并且将晶片退火以在非氧化环境中形成接合晶片。所形成的键合键主要是硅与硅和硅与碳键。

7. 发明授权

US5517047A Bonded wafer processing 失效
标题翻译：粘合晶片加工
公开(公告)号：US5517047A
公开(公告)日：1996-05-14
申请号：US287773
申请日：1994-08-09
申请人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller , William H. Speece
发明人： Jack H. Linn , Robert K. Lowry , George V. Rouse , James F. Buller , William H. Speece
IPC分类号： H01L21/20 , H01L21/762 , H01L27/01
CPC分类号： H01L21/2007 , H01L21/76264 , H01L21/76275 , H01L21/76283 , H01L21/76286 , Y10S148/012 , Y10S438/92
摘要： Low temperature wafer bonding using a silicon-oxidizing bonding liquid permits introduction of radiation hardening dopants and electrically active dopants as constituents of the bonding liquid. Oxidizers such as nitric acid may be used in the bonding liquid. Dielectric layers on the device wafer and the handle wafer may be used when additional silicon is provided for the oxidative bonding. Integrated circuits fabricated from such bonded wafers may have buried layers and radiation hardening with device silicon too thick for implantation.
摘要翻译：使用硅氧化粘合液的低温晶片接合允许引入辐射固化掺杂剂和电活性掺杂剂作为粘合液的成分。可以在粘合液中使用硝酸等氧化剂。当为氧化粘合提供额外的硅时，可以使用器件晶片和处理晶片上的介电层。由这种接合晶片制造的集成电路可能具有掩埋层和放射硬化，器件硅太厚以用于植入。

8. 发明授权

US5240876A Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process 失效
标题翻译：在BESOI工艺中制造具有SiGe作为回蚀膜的SOI晶片的方法
公开(公告)号：US5240876A
公开(公告)日：1993-08-31
申请号：US891910
申请日：1992-06-01
申请人： Stephen J. Gaul , George V. Rouse
发明人： Stephen J. Gaul , George V. Rouse
IPC分类号： H01L21/20 , H01L21/322 , H01L21/762 , H01L29/786
CPC分类号： H01L21/3226 , H01L21/2007 , H01L21/76251 , H01L29/78603 , Y10S438/904
摘要： An SOI wafer is formed having a silicon-germanium layer between the epitaxial layer of the device and the insulative layer. The process includes bonding a second substrate to a silicon-germanium layer on a first substrate by an intermediate insulative layer. The first substrate is removed down to the silicon-germanium layer and the silicon layer is epitaxially formed on the silicon-germanium layer.
摘要翻译：形成在器件的外延层和绝缘层之间具有硅 - 锗层的SOI晶片。该方法包括通过中间绝缘层将第二衬底接合在第一衬底上的硅 - 锗层上。将第一衬底除去到硅 - 锗层，并且在硅 - 锗层上外延形成硅层。

9. 发明授权

US5034343A Manufacturing ultra-thin wafer using a handle wafer 失效
标题翻译：制造使用手柄晶圆的超薄晶圆
公开(公告)号：US5034343A
公开(公告)日：1991-07-23
申请号：US490316
申请日：1990-03-08
申请人： George V. Rouse , Paul S. Reinecke , Craig J. McLachlan
发明人： George V. Rouse , Paul S. Reinecke , Craig J. McLachlan
IPC分类号： H01L21/20 , H01L21/762
CPC分类号： H01L21/2007 , H01L21/76251 , Y10S148/135
摘要： A process including bonding a first device wafer to a handle wafer by an intermediate bonding oxide layer and thinning the device wafer to not greater than 7 mils. An epitaxial device layer of under 1 mil may be added. Device formation steps are performed on a first surface of the first device wafer. This is followed by removing the handle wafer to produce a resulting wafer having substantially the thickness of the first device layer. To produce a silicon on insulator (SOI), a third device wafer is bonded to the first surface of the first device wafer by the intermediate oxide layer and the third wafer is thinned to not greater than 40 microns. The first and third device wafers form the resulting SOI wafer.
摘要翻译：一种方法，包括通过中间结合氧化物层将第一器件晶片接合到处理晶片，并将器件晶片减薄到不大于7密耳。可以加入1密耳以下的外延装置层。在第一器件晶片的第一表面上执行器件形成步骤。然后移除手柄晶片以产生具有基本上第一器件层厚度的所得晶片。为了制造绝缘体上硅（SOI），第三器件晶片通过中间氧化物层结合到第一器件晶片的第一表面，并将第三晶片减薄到不大于40微米。第一和第三器件晶片形成所得的SOI晶片。

10. 发明授权

US07052973B2 Bonded substrate for an integrated circuit containing a planar intrinsic gettering zone 失效
标题翻译：用于包含平面固有吸气区的集成电路的粘合衬底
公开(公告)号：US07052973B2
公开(公告)日：2006-05-30
申请号：US10811617
申请日：2004-03-29
申请人： Jack H. Linn , William H. Speece , Michael G. Shlepr , George V. Rouse
发明人： Jack H. Linn , William H. Speece , Michael G. Shlepr , George V. Rouse
IPC分类号： H01L21/46 , H01L21/30
CPC分类号： H01L21/3226 , H01L21/2007 , H01L21/76251 , Y10S438/977
摘要： A bonded semiconductor-on-insulator substrate for an integrated circuit. The bonded semiconductor-on-insulator substrate includes a wafer, a handle wafer and an insulating bond layer. The wafer has a first layer of monocrystalline semiconductor material adjacent a first surface of the wafer. The wafer also has a second layer of undamaged by implantation monocrystalline semiconductor material adjacent a second surface of the wafer. The wafer further has a substantially planar intrinsic gettering zone of substantially pure semiconductor material and active gettering sites positioned between the first and second layers formed by implanting ions of the semiconductor material through the first layer of monocrystalline semiconductor material. The insulating bond layer bonds the handle wafer to the first surface of the wafer.
摘要翻译：一种用于集成电路的绝缘键合半导体衬底。粘结绝缘体上的半导体衬底包括晶片，手柄晶片和绝缘结合层。晶片具有与晶片的第一表面相邻的第一单晶半导体材料层。晶片还具有与晶片的第二表面相邻的注入单晶半导体材料未损坏的第二层。晶片还具有基本上平坦的基本纯净的半导体材料的吸杂区和位于通过将半导体材料的离子注入第一层单晶半导体材料而形成的第一和第二层之间的主动吸气位置。绝缘结合层将处理晶片结合到晶片的第一表面。

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