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1. 发明授权

US07687370B2 Method of forming a semiconductor isolation trench 有权
标题翻译：形成半导体隔离沟槽的方法
公开(公告)号：US07687370B2
公开(公告)日：2010-03-30
申请号：US11342102
申请日：2006-01-27
申请人： Toni D. Van Gompel , John J. Hackenberg , Rode R. Mora , Suresh Venkatesan
发明人： Toni D. Van Gompel , John J. Hackenberg , Rode R. Mora , Suresh Venkatesan
IPC分类号： H01L21/76 , H01L21/311 , H01L21/302
CPC分类号： H01L21/76224 , Y10S438/911
摘要： A method for forming a semiconductor isolation trench includes forming a pad oxide layer over a substrate and forming a barrier layer over the substrate. A masking layer is formed over the barrier layer and is patterned to form at least one opening in the masking layer. At least a part of the barrier layer and at least a part of the pad oxide layer are etched through the at least one opening resulting in a trench pad oxide layer. Etching of the trench pad oxide layer stops substantially at a top surface of the substrate within the isolation trench. An oxide layer is grown by diffusion on at least the top surface of the substrate corresponding to the at least one isolation trench. The method further includes etching the oxide layer and at least a portion of the substrate to form at least one isolation trench opening.
摘要翻译：用于形成半导体隔离沟槽的方法包括在衬底上形成衬垫氧化物层，并在衬底上形成阻挡层。掩模层形成在阻挡层之上，并被图案化以在掩模层中形成至少一个开口。阻挡层的至少一部分和衬垫氧化物层的至少一部分被蚀刻穿过至少一个开口，导致沟槽衬垫氧化物层。沟槽衬垫氧化物层的蚀刻基本上在隔离沟槽内的衬底顶表面上停止。氧化物层通过扩散至少对应于至少一个隔离沟槽的衬底的顶表面生长。所述方法还包括蚀刻所述氧化物层和所述衬底的至少一部分以形成至少一个隔离沟槽开口。

2. 发明授权

US07097714B2 Particulate removal from an electrostatic chuck 失效
标题翻译：从静电吸盘去除颗粒
公开(公告)号：US07097714B2
公开(公告)日：2006-08-29
申请号：US10740171
申请日：2003-12-18
申请人： John J. Hackenberg
发明人： John J. Hackenberg
IPC分类号： B08B5/04
CPC分类号： H01L21/67028 , B08B5/02 , H01L21/6831
摘要： The cleaning of particles from an electrostatic chuck. In one embodiment, a method of cleaning an electrostatic chuck in a processing chamber is disclosed. The method comprises directing a flow of gas across the electrostatic chuck to dislodge particles from the electrostatic chuck and removing the flow of gas and particles through an exhaust port in the processing chamber. In this embodiment, the vacuum integrity of the chamber is not compromised during the cleaning of the electrostatic chuck.
摘要翻译：从静电吸盘清洁颗粒。在一个实施例中，公开了一种在处理室中清洁静电卡盘的方法。该方法包括引导气流穿过静电吸盘以从静电吸盘排出颗粒，并通过处理室中的排气口去除气体和颗粒的流动。在该实施例中，在清洁静电卡盘期间腔室的真空完整性不受影响。

3. 发明授权

US5830279A Device and method for improving corrosion resistance and etch tool integrity in dry metal etching 失效
标题翻译：在干金属蚀刻中提高耐蚀性和蚀刻工具完整性的装置和方法
公开(公告)号：US5830279A
公开(公告)日：1998-11-03
申请号：US536257
申请日：1995-09-29
申请人： John J. Hackenberg
发明人： John J. Hackenberg
IPC分类号： B08B7/00 , H01L21/00 , H01L21/02 , H01L21/3213 , B08B6/00 , B44C1/22
CPC分类号： H01L21/02071 , B08B7/0071 , H01L21/67028 , H01L21/67115
摘要： A device and method for removing contaminants from semiconductor wafers and from the interior of wafer processing chambers in which the temperature inside the chambers is raised to sufficiently high levels for short time periods. In a wafer etching chamber, heat cleaning is performed after wafer removal and lessens the required frequency of other cleaning methods and in doing so reduces the time the chamber is unavailable. In a mask removal chamber, heat cleaning is performed with the wafer in the chamber and while still under vacuum conditions, thereby driving contaminants off of both the wafer and the chamber interior. The wafer cleaning is performed prior to exposure to atmospheric water vapor which can initiate corrosion.
摘要翻译：一种用于从半导体晶片和晶片处理室内部去除污染物的装置和方法，其中室内温度在短时间内升高到足够高的水平。在晶片蚀刻室中，在晶片去除之后进行热清洗，并减少所需的其它清洁方法的频率，并且这样做减少了室不可用的时间。在掩模去除室中，用晶片在室中进行热清洗，同时在真空条件下进行热清洗，从而将杂质从晶片和室内驱动。在暴露于可能引发腐蚀的大气水汽之前进行晶片清洗。

4. 发明授权

US08258035B2 Method to improve source/drain parasitics in vertical devices 有权
标题翻译：在垂直设备中改善源极/漏极寄生效应的方法
公开(公告)号：US08258035B2
公开(公告)日：2012-09-04
申请号：US11800204
申请日：2007-05-04
申请人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
发明人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L21/26513 , H01L21/2658 , H01L29/66803 , H01L29/785
摘要： A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
摘要翻译：提供一种制造晶体管的方法，其包括：（a）提供半导体结构，所述半导体结构具有覆盖半导体层（203）的栅极（211），并且具有邻近所述栅极设置的至少一个间隔结构（213）（b）去除与间隔结构相邻的半导体结构的一部分，从而暴露位于间隔结构下面的半导体结构的部分（215）; 和（c）将半导体结构的暴露部分经受成角度的植入物（253,254）。

5. 发明授权

US5648678A Programmable element in barrier metal device 失效
标题翻译：阻挡金属器件中的可编程元件
公开(公告)号：US5648678A
公开(公告)日：1997-07-15
申请号：US310280
申请日：1994-09-21
申请人： Patrick A. Begley , John T. Gasner , Lawrence G. Pearce , Choong S. Rhee , Jeanne M. McNamara , John J. Hackenberg , Donald F. Hemmenway
发明人： Patrick A. Begley , John T. Gasner , Lawrence G. Pearce , Choong S. Rhee , Jeanne M. McNamara , John J. Hackenberg , Donald F. Hemmenway
IPC分类号： H01L23/525 , H01L27/102 , H01L29/00
CPC分类号： H01L27/1021 , H01L23/5252 , H01L2924/0002 , Y10S257/926
摘要： An integrated circuit 10 has a programmable Zener diode with diffusion regions 18 and 16 and metal contacts 34 and 32. A barrier metal 30 is disposed between one contact 32 and the substrate 12; another contact region 18 has no barrier metal on its surface. A polysilicon layer 22 is self-aligned with surface regions 18 and diffusion region 18. A silicide layer 128 may be used on the polysilicon layer 22 and on surface region 18.
摘要翻译：集成电路10具有可扩展区域18和16以及金属触点34和32的可编程齐纳二极管。阻挡金属30设置在一个触点32和基板12之间; 另一个接触区域18在其表面上没有阻挡金属。多晶硅层22与表面区域18和扩散区域18自对准。硅化物层128可以用在多晶硅层22上和表面区域18上。

6. 发明授权

US07972922B2 Method of forming a semiconductor layer 有权
标题翻译：形成半导体层的方法
公开(公告)号：US07972922B2
公开(公告)日：2011-07-05
申请号：US12275659
申请日：2008-11-21
申请人： Hunter J. Martinez , John J. Hackenberg , Jill Hildreth , Ross E. Noble
发明人： Hunter J. Martinez , John J. Hackenberg , Jill Hildreth , Ross E. Noble
IPC分类号： H01L21/8238
CPC分类号： H01L31/1804 , H01L31/103 , H01L31/1864 , Y02E10/547 , Y02P70/521
摘要： A method of forming a semiconductor layer, which in one embodiment is part of a photodetector, includes forming a silicon shape, applying ozonated water, removing the first oxide layer at a temperature below 600 degrees Celsius, and epitaxially growing germanium. The silicon shape has a top surface that is exposed. The ozonated water is applied to the top surface and causes formation of a first oxide layer on the top surface. The germanium is grown on the top surface.
摘要翻译：一种形成半导体层的方法，其在一个实施例中是光电检测器的一部分，包括形成硅形状，施加臭氧水，在低于600摄氏度的温度下去除第一氧化物层，以及外延生长锗。硅形状具有暴露的顶面。臭氧水被施加到顶部表面并且在顶部表面上形成第一氧化物层。锗在顶面生长。

7. 发明授权

US07528029B2 Stressor integration and method thereof 有权
标题翻译：应力集成及其方法
公开(公告)号：US07528029B2
公开(公告)日：2009-05-05
申请号：US11408347
申请日：2006-04-21
申请人： Paul A. Grudowski , Darren V. Goedekc , John J. Hackenberg
发明人： Paul A. Grudowski , Darren V. Goedekc , John J. Hackenberg
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/7843 , H01L2924/0002 , H01L2924/00
摘要： A method is provided for making a semiconductor device. In accordance with the method, a substrate (203) is provided which has first (205) and second (207) gate structures thereon. A first stressor layer (215) is formed over the substrate, and a sacrificial layer (216) is formed over the first stressor layer. A second stressor layer (219) is formed over the sacrificial layer.
摘要翻译：提供了制造半导体器件的方法。根据该方法，提供在其上具有第一（205）和第二（207）门结构的衬底（203）。第一应力层（215）形成在衬底上，牺牲层（216）形成在第一应激层上。在牺牲层上形成第二应力层（219）。

8. 发明申请

US20080274600A1 Method to improve source/drain parasitics in vertical devices 有权
标题翻译：在垂直设备中改善源极/漏极寄生效应的方法
公开(公告)号：US20080274600A1
公开(公告)日：2008-11-06
申请号：US11800204
申请日：2007-05-04
申请人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
发明人： Leo Mathew , John J. Hackenberg , David C. Sing , Tab A. Stephens , Daniel G. Tekleab , Vishal P. Trivedi
IPC分类号： H01L21/00
CPC分类号： H01L21/26586 , H01L21/26513 , H01L21/2658 , H01L29/66803 , H01L29/785
摘要： A method for making a transistor is provided which comprises (a) providing a semiconductor structure having a gate (211) overlying a semiconductor layer (203), and having at least one spacer structure (213) disposed adjacent to said gate; (b) removing a portion of the semiconductor structure adjacent to the spacer structure, thereby exposing a portion (215) of the semiconductor structure which underlies the spacer structure; and (c) subjecting the exposed portion of the semiconductor structure to an angled implant (253, 254).
摘要翻译：提供一种制造晶体管的方法，其包括：（a）提供半导体结构，所述半导体结构具有覆盖半导体层（203）的栅极（211），并且具有邻近所述栅极设置的至少一个间隔结构（213）（b）去除与间隔结构相邻的半导体结构的一部分，从而暴露位于间隔结构下面的半导体结构的部分（215）; 和（c）将半导体结构的暴露部分经受成角度的植入物（253,254）。

9. 发明授权

US06455379B2 Power trench transistor device source region formation using silicon spacer 失效
标题翻译：使用硅衬垫的功率沟槽晶体管器件源区域形成
公开(公告)号：US06455379B2
公开(公告)日：2002-09-24
申请号：US09799845
申请日：2001-03-06
申请人： Linda S. Brush , Jun Zeng , John J. Hackenberg , Jack H. Linn , George V. Rouse
发明人： Linda S. Brush , Jun Zeng , John J. Hackenberg , Jack H. Linn , George V. Rouse
IPC分类号： H01L21336
CPC分类号： H01L29/7802 , H01L29/41766 , H01L29/66348 , H01L29/66378 , H01L29/66545 , H01L29/7397 , H01L29/749 , H01L29/7813
摘要： A power trench MOS-gated transistor is constructed with a buried gate to source dielectric inside a gate trench region. In the innovative device, a thick oxide (grown or deposited) is used to define the height of the trench walls. A body region is initially formed by selective epitaxial growth and etch back. Source regions are formed also by selective epitaxial growth. The body is finally formed by selective epitaxial growth and etch back. The oxide is removed from the trench, the trench walls are oxidized to form a gate oxide, and doped polysilicon fills the trench to form a gate. By the formation of the source region using the spacer etch, this process simplifies the fabrication of power trench gated devices, and provides for increased contact surface area without increasing device size.
摘要翻译：功率沟槽MOS门控晶体管由栅极沟槽区域内的栅极源极构成。在创新的设备中，使用厚的氧化物（生长或沉积）来限定沟槽壁的高度。最初通过选择性外延生长和回蚀而形成体区。源区也通过选择性外延生长形成。身体最终通过选择性外延生长和回蚀而形成。从沟槽去除氧化物，沟槽壁被氧化以形成栅极氧化物，并且掺杂多晶硅填充沟槽以形成栅极。通过使用间隔物蚀刻形成源极区域，该工艺简化了功率沟槽门控器件的制造，并且提供了增加的接触表面积而不增加器件尺寸。

10. 发明申请

US20100129952A1 METHOD OF FORMING A SEMICONDUCTOR LAYER 有权
标题翻译：形成半导体层的方法
公开(公告)号：US20100129952A1
公开(公告)日：2010-05-27
申请号：US12275659
申请日：2008-11-21
申请人： Hunter J. Martinez , John J. Hackenberg , Jill Hildreth , Ross E. Noble
发明人： Hunter J. Martinez , John J. Hackenberg , Jill Hildreth , Ross E. Noble
IPC分类号： H01L31/18
CPC分类号： H01L31/1804 , H01L31/103 , H01L31/1864 , Y02E10/547 , Y02P70/521
摘要： A method of forming a semiconductor layer, which in one embodiment is part of a photodetector, includes forming a silicon shape, applying ozonated water, removing the first oxide layer at a temperature below 600 degrees Celsius, and epitaxially growing germanium. The silicon shape has a top surface that is exposed. The ozonated water is applied to the top surface and causes formation of a first oxide layer on the top surface. The germanium is grown on the top surface.
摘要翻译：一种形成半导体层的方法，其在一个实施例中是光电检测器的一部分，包括形成硅形状，施加臭氧水，在低于600摄氏度的温度下去除第一氧化物层，以及外延生长锗。硅形状具有暴露的顶面。臭氧水被施加到顶部表面并且在顶部表面上形成第一氧化物层。锗在顶面生长。

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