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1. 发明授权

US06946897B2 Technique for measuring temperature and current via a MOSFET of a synchronous buck voltage converter 失效
公开(公告)号：US06946897B2
公开(公告)日：2005-09-20
申请号：US10691370
申请日：2003-10-22
申请人： Lawrence G. Pearce
发明人： Lawrence G. Pearce
IPC分类号： G01K7/01 , H02M3/158 , H03K3/42
CPC分类号： G01K7/01 , H02M3/1588 , H02M2001/0009 , Y02B70/1466
摘要： In order to derive a precise measurement of temperature and current in a synchronous buck DC-DC converter a synchronous conduction cycle measurement of the value of reverse conduction voltage (VON), and an asynchronous conduction cycle measurement of the value of body diode conduction voltage (VDF) of the low side power MOSFET are performed. These two measured values are then used as dual inputs to a two-dimensional to two-dimensional transform function (e.g., look-up table) that is effective to map the measured voltage values into output values for current (I) and temperature (T).

2. 发明授权

US06791304B2 Electronic device including multiphase switching regulator and related methods 失效
标题翻译：电子器件包括多相开关调节器及相关方法
公开(公告)号：US06791304B2
公开(公告)日：2004-09-14
申请号：US10350755
申请日：2003-01-24
申请人： Lawrence G. Pearce , Nicolaas W. Van Vonno
发明人： Lawrence G. Pearce , Nicolaas W. Van Vonno
IPC分类号： G05F1618
CPC分类号： H02J1/102 , H02M3/1584
摘要： An electronic device may include a circuit board, at least one load circuit carried by the circuit board, and a power distribution conductor carried by the circuit board and connected to the at least one load circuit. The electronic device may also include a multiphase switching regulator including a plurality of output stages connected to the power distribution conductor, and a controller for controlling the output stages based upon respective phase currents. The respective phase currents may be derived from corresponding voltage drops across the power distribution conductor and a matrix of resistivity values.
摘要翻译：电子设备可以包括电路板，由电路板承载的至少一个负载电路和由电路板承载并连接到至少一个负载电路的配电导体。电子设备还可以包括多相开关调节器，其包括连接到配电导体的多个输出级，以及用于基于各自的相电流来控制输出级的控制器。相应的相电流可以从功率分布导体上的相应电压降和电阻率值矩阵导出。

3. 发明授权

US5973368A Monolithic class D amplifier 失效
标题翻译：单片D类放大器
公开(公告)号：US5973368A
公开(公告)日：1999-10-26
申请号：US973769
申请日：1997-12-11
申请人： Lawrence G. Pearce , Donald F. Hemmenway
发明人： Lawrence G. Pearce , Donald F. Hemmenway
IPC分类号： H03F99/00 , H01L21/8249 , H01L27/02 , H01L27/06 , H03F1/52 , H03F3/217 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/8234 , H01L21/8249 , H01L27/0207 , H01L27/0623 , H01L27/0922 , H01L29/0696 , H01L29/4238 , H01L29/66719 , H01L29/7809 , H01L29/7811 , H01L29/7815 , H03F1/523 , H03F3/187 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/72 , H01L29/0615 , H01L29/1095 , H01L29/456 , H01L29/665
摘要： A monolithic integrated circuit is mounted in a speaker cabinet to drive the voice coil of the speaker. The monolithic integrated circuit may be a class D amplifier and is at least a half bridge or full bridge power MOSFET device. Structures comprise MOS switching devices of the bridge driver and N+ buried layer of the QVDMOS transistors of the bridge circuits.
摘要翻译： PCT No.PCT / US96 / 08826 Sec。 371日期：1998年7月27日 102（e）1998年7月27日PCT PCT 1996年6月5日PCT公布。公开号WO96 / 41412 PCT 日期1996年12月19日将单片集成电路安装在扬声器箱中以驱动扬声器的音圈。单片集成电路可以是D类放大器，并且是至少一个半桥或全桥功率MOSFET器件。结构包括桥式驱动器的MOS开关器件和桥式电路的QVDMOS晶体管的N +掩埋层。

4. 发明授权

US4829359A CMOS device having reduced spacing between N and P channel 失效
标题翻译： CMOS器件具有减小N和P沟道之间的间隔
公开(公告)号：US4829359A
公开(公告)日：1989-05-09
申请号：US55558
申请日：1987-05-29
申请人： Kenneth K. O , Lawrence G. Pearce , Dyer A. Matlock
发明人： Kenneth K. O , Lawrence G. Pearce , Dyer A. Matlock
IPC分类号： H01L27/092
CPC分类号： H01L27/0927
摘要： The separation constraint between the respective junctions formed between the drain regions of the complementary transistors and the semiconductor material in which they are formed is obviated by a structure which permits the respective drain regions of the opposite conductivity type transistors to have a reduced (effecting to zero) mutual separation and, at the same time, prevent the depletion regions fomed between the junctions defined by these source regions and the semiconductor material in which they are formed from spreading into contact with one another and thereby shorting the transistors together. This objective is achieved by a structure in which the source regions of the respective P and N channel transistors are formed so as to directly abut against one another and to be contiguous with a layer of buried dielectric isolation therebeneath. The buried dielectric layer extends from the bottom portions of the drain regions to a prescribed depth in each of the P-well region and the N-type substrate, so as to effectively provide a barrier between depletion region associated with the junction defined by the P well and N substrate the depletion regions formed between the N+ drain region and the P-well and the P+ drain region and the N-type substrate.
摘要翻译：在互补晶体管的漏极区域和形成它们的半导体材料之间形成的各个结之间的分离约束被允许相反导电型晶体管的相应漏极区域减小（影响为零）的结构所消除）相互分离，并且同时防止由这些源极区域限定的结与其形成的半导体材料之间的耗尽区域彼此扩散接触，从而将晶体管短路。该目的是通过这样的结构实现的：其中，各个P沟道晶体管和N沟道晶体管的源极区域形成为彼此直接邻接并且与其旁边的埋入介质隔离层邻接。掩埋电介质层从漏极区域的底部延伸到每个P阱区域和N型衬底中规定的深度，从而有效地提供与由P形成的连接点相关联的耗尽区域之间的势垒阱和N衬底在N +漏极区和P阱以及P +漏极区和N型衬底之间形成的耗尽区。

5. 发明授权

US4702000A Technique for elimination of polysilicon stringers in direct moat field oxide structure 失效
公开(公告)号：US4702000A
公开(公告)日：1987-10-27
申请号：US841297
申请日：1986-03-19
申请人： Dyer A. Matlock , Richard L. Lichtel, Jr. , Lawrence G. Pearce
发明人： Dyer A. Matlock , Richard L. Lichtel, Jr. , Lawrence G. Pearce
IPC分类号： H01L21/28 , H01L21/336 , H01L21/762 , H01L21/265 , H01L21/22
CPC分类号： H01L29/66575 , H01L21/28123 , H01L21/762 , Y10S148/05 , Y10S148/086 , Y10S148/122 , Y10S148/131 , Y10S438/978
摘要： The problem of unwanted residual polysilicon stringers along the sidewalls of a field oxide layer employed in direct moat wafer processing is avoided by a processing scheme in which the sidewalls of the aperture in the field oxide layer are initially tapered prior to formation of the polysilicon layer to be used for the gate electrode(s). Because of the graduated thickness of the sidewalls of the field oxide layer, the thickness of the polysilicon layer formed thereon is substantially uniform over the entirety of the substrate. As a result, during subsequent masking of the polysilicon layer to define the gate electrode(s), all unmasked portions of the polysilicon are completely etched, leaving no residual material (e.g. stringers) that could be a source of device contamination. After the polysilicon gate has been delineated, the sloped sidewalls of the field oxide are removed (by anisotropic etching), so that the sidewalls of the apertures or windows of the field oxide layer will be perpendicular to the planar surface of the substrate, thus facilitating proper formation of dielectric (oxide) spacers therealong, which thereby provide separation between contact materials and the junction created by shallow ion implantation of dopants through the field oxide aperture.

6. 发明授权

US06819190B2 Robust fractional clock-based pulse generator for digital pulse width modulator 有权
$Robust fractional clock-based pulse generator for digital pulse width modulator$
公开(公告)号：US06819190B2
公开(公告)日：2004-11-16
申请号：US10315836
申请日：2002-12-10
申请人： Lawrence G. Pearce , William David Bartlett
发明人： Lawrence G. Pearce , William David Bartlett
IPC分类号： H03B2700
CPC分类号： H03L7/0805 , H03K5/06 , H03K7/08 , H03L7/0812
摘要： A tapped delay line generates a fractional clock pulse signal for controlling a PWM pulse generator, such as used in a DC-DC converter. Operational parameters of the tapped delay are adjusted to maintain a desired fractional precision of the duty-cycle of the PWM clock pulse signal. In a first, phase locked loop (PLL) based embodiment, the tapped delay line-based digital PWM pulse generator includes a compensating phase locked-loop formed around an auxiliary tapped delay line that implements the voltage controlled oscillator of the PLL. In a second embodiment, the PWM pulse generator is configured as an ‘open-loop’ tapped delay line phase detector architecture, which avoids having to correlate parameters of the PLL delay line with those of the PWM delay line.

7. 发明授权

US06812108B2 BICMOS process with low temperature coefficient resistor (TCRL) 失效
标题翻译： BICMOS工艺采用低温系数电阻（TCRL）
公开(公告)号：US06812108B2
公开(公告)日：2004-11-02
申请号：US10393181
申请日：2003-03-19
申请人： Donald Hemmenway , Jose Delgado , John Butler , Anthony Rivoli , Michael D. Church , George V. Rouse , Lawrence G. Pearce , George Bajor
发明人： Donald Hemmenway , Jose Delgado , John Butler , Anthony Rivoli , Michael D. Church , George V. Rouse , Lawrence G. Pearce , George Bajor
IPC分类号： H01L2120
CPC分类号： H01L28/20 , H01L21/763 , H01L21/8249 , H01L27/0635
摘要： A low temperature coefficient resistor(TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations. A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient. A process for fabrication of the resistor is used which combines separate spacer oxide depositions, provides buried layers having different diffusion coefficients, incorporates dual dielectric trench sidewalls that double as a polish stop, supplies a spacer structure that controls precisely the emitter-base dimension, and integrates bipolar and CMOS devices with negligible compromise to the features of either type.
摘要翻译：低温度系数电阻（TCRL）具有一些未修复的离子注入损伤。损坏部分会提高电阻，使电阻对工作温度波动较不敏感。多晶硅薄膜低温系数电阻器和电阻器制造方法克服了现有技术的电阻系数问题，同时消除了BiCMOS制造工艺的步骤，优化了双极设计的权衡，改善了无源器件隔离。在绝缘层（通常为二氧化硅或氮化硅）上形成电阻电阻器（TCRL）的低温度系数，该层包含具有相对高浓度的一种或多种物质的掺杂剂的多晶硅。对于注入电阻器而言，使用退火工艺，其比典型的现有技术的注入电阻器的退火工艺短，从而在电阻器中留下一些有意的未退火损坏。计划的损坏使TCRL具有更高的阻力，而不增加其温度系数。使用制造电阻器的方法，其组合分开的间隔氧化物沉积，提供具有不同扩散系数的掩埋层，并入双重介质沟槽侧壁作为抛光停止点，提供精确控制发射极基底尺寸的间隔结构，以及将双极和CMOS器件集成到任何一种类型的特性上都可忽略不计。

8. 发明授权

US06798024B1 BiCMOS process with low temperature coefficient resistor (TCRL) 失效
标题翻译： BiCMOS工艺与低温系数电阻（TCRL）
公开(公告)号：US06798024B1
公开(公告)日：2004-09-28
申请号：US09607080
申请日：2000-06-29
申请人： Donald Hemmenway , Jose Delgado , John Butler , Anthony Rivoli , Michael D. Church , George V. Rouse , Lawrence G. Pearce , George S. Bajor
发明人： Donald Hemmenway , Jose Delgado , John Butler , Anthony Rivoli , Michael D. Church , George V. Rouse , Lawrence G. Pearce , George S. Bajor
IPC分类号： H01L2976
CPC分类号： H01L28/20 , H01L21/763 , H01L21/8249 , H01L27/0635
摘要： A low temperature coefficient resistor (TCRL) has some unrepaired ion implant damage. The damaged portion raises the resistance and renders the resistor less sensitive to operating temperature fluctuations A polysilicon thin film low temperature coefficient resistor and a method for the resistor's fabrication overcomes the coefficient of resistance problem of the prior art, while at the same time eliminating steps from the BiCMOS fabrication process, optimizing bipolar design tradeoffs, and improving passive device isolation. A low temperature coefficient of resistance resistor (TCRL) is formed on a layer of insulation, typically silicon dioxide or silicon nitride, the layer comprising polysilicon having a relatively high concentration of dopants of one or more species. An annealing process is used for the implanted resistor which is shorter than that for typical prior art implanted resistors, leaving some intentional unannealed damage in the resistor. The planned damage gives the TCRL a higher resistance without increasing its temperature coefficient. A process for fabrication of the resistor is used which combines separate spacer oxide depositions, provides buried layers having different diffusion coefficients, incorporates dual dielectric trench sidewalls that double as a polish stop, supplies a spacer structure that controls precisely the emitter-base dimension, and integrates bipolar and CMOS devices with negligible compromise to the features of either type.
摘要翻译：低温度系数电阻（TCRL）具有一些未修复的离子注入损伤。损坏部分提高电阻并使电阻器对工作温度波动较不敏感多晶硅薄膜低温度系数电阻器和电阻器制造方法克服了现有技术的电阻问题系数，同时消除了步骤 BiCMOS制造工艺，优化双极设计权衡，改善无源器件隔离。在绝缘层（通常为二氧化硅或氮化硅）上形成电阻电阻器（TCRL）的低温度系数，该层包含具有相对高浓度的一种或多种物质的掺杂剂的多晶硅。对于注入电阻器而言，使用退火工艺，其比典型的现有技术的注入电阻器的退火工艺短，从而在电阻器中留下一些有意的未退火损坏。计划的损坏使TCRL具有更高的阻力，而不增加其温度系数。使用制造电阻器的方法，其组合分开的间隔氧化物沉积，提供具有不同扩散系数的掩埋层，并入双重介质沟槽侧壁作为抛光停止点，提供精确控制发射极基底尺寸的间隔结构，以及将双极和CMOS器件集成到任何一种类型的特性上都可忽略不计。

9. 发明授权

US5580816A Local oxidation process for high field threshold applications 失效
标题翻译：用于高场阈值应用的局部氧化工艺
公开(公告)号：US5580816A
公开(公告)日：1996-12-03
申请号：US481116
申请日：1995-06-07
申请人： Donald F. Hemmenway , Lawrence G. Pearce
发明人： Donald F. Hemmenway , Lawrence G. Pearce
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/762 , H01L21/76216
摘要： A method for electrically isolating semiconductor devices in an integrated circuit structure with high field threshold, low defect level regions. The semiconductor structure includes a device layer predominantly comprising lattice silicon with a surface suitable for device formation. Multiple device regions are defined and field regions are defined for electrically isolating the device regions from one another. Dopant species are implanted to create a channel stop adjacent two of the device regions. The implant is of sufficient energy and concentration to impart within the device layer nucleation sites of the type known to result in stacking faults during oxide growth conditions. A thickness of thermally grown silicon dioxide is formed in the field regions by first thermally processing the integrated circuit structure to remove nucleation sites from the device layer and form a minor portion of the field oxide thickness. Subsequently a major portion of the oxide thickness is formed under relatively fast growth conditions.
摘要翻译：一种用于在具有高场阈值，低缺陷水平区域的集成电路结构中电绝缘半导体器件的方法。半导体结构包括主要包括具有适于器件形成的表面的晶格硅的器件层。定义了多个器件区域，并且限定了用于将器件区域彼此电隔离的场区域。植入掺杂物质以在相邻两个器件区域之间产生通道阻挡。植入物具有足够的能量和浓度以赋予在氧化物生长条件下已知导致堆垛层错的类型的器件层成核位点。通过首先热处理集成电路结构以从器件层去除成核位置并形成场氧化物厚度的一小部分，在场区中形成热生长二氧化硅的厚度。随后在相对较快的生长条件下形成氧化物厚度的主要部分。

10. 发明授权

US5567978A High voltage, junction isolation semiconductor device having dual conductivity tape buried regions and its process of manufacture 失效
标题翻译：具有双导电带掩埋区域的高压，结隔离半导体器件及其制造工艺
公开(公告)号：US5567978A
公开(公告)日：1996-10-22
申请号：US383261
申请日：1995-02-03
申请人： Lawrence G. Pearce
发明人： Lawrence G. Pearce
IPC分类号： H01L21/331 , H01L21/74 , H01L21/761 , H01L29/00
CPC分类号： H01L29/66272 , H01L21/74 , H01L21/761 , Y10S148/01 , Y10S148/011
摘要： A two masking level process for a dual buried region epitaxial architecture forms a first masking layer on a surface of a P type substrate. The first masking layer exposes first and second surface portions of the substrate for N+ and P+ buried regions. N type impurities are introduced into the substrate through the first masking layer, so as to form N+ doped regions. A second masking layer is then selectively formed on the first masking layer, such that the second masking layer masks the first aperture, but exposes a second portion of the first masking layer that both includes and surrounds the second aperture. Boron impurities are then introduced through the exposed second aperture of the first masking layer, to a P+ doping concentration. That portion of the first masking layer surrounding the second aperture is removed, and boron impurities are then introduced into exposed second and third surface portions of the substrate, thereby forming a third buried region of the second conductivity type that is adjacent to the second doped region. The composite mask is removed from the substrate, and an N type layer is grown. Due to differences in diffusion coefficients, the P dopant (boron) in the second and third buried regions outruns the N dopant in the second buried region, resulting in the formation of an N+ buried region that is encapsulated in a P+ buried region. The P+ buried region is, in turn, laterally surrounded by a P-type buried region, so as to provide the desired compensation of N ions that are autodoped from the first N+ buried region in the epitaxial layer.
摘要翻译：用于双掩埋区域外延结构的两个掩模级处理在P型衬底的表面上形成第一掩模层。第一掩蔽层暴露衬底的第一和第二表面部分用于N +和P +掩埋区域。通过第一掩模层将N型杂质引入衬底中，以形成N +掺杂区域。然后在第一掩蔽层上选择性地形成第二掩模层，使得第二掩蔽层掩蔽第一孔，但暴露第一掩蔽层的第二部分，其包括并包围第二孔。然后将硼杂质通过第一掩模层的暴露的第二孔引入P +掺杂浓度。去除围绕第二孔的第一掩蔽层的那部分，然后将硼杂质引入衬底的暴露的第二和第三表面部分中，从而形成与第二掺杂区相邻的第二导电类型的第三掩埋区。从衬底上去除复合掩模，并生长N型层。由于扩散系数的差异，第二和第三掩埋区域中的P掺杂剂（硼）超出第二掩埋区域中的N掺杂剂，导致形成封装在P +掩埋区域中的N +掩埋区域。 P +掩埋区又被P型掩埋区横向围绕，从而提供从外延层中的第一N +掩埋区自动掺杂的N离子的期望补偿。

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