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1. 发明授权

US06506676B2 Method of manufacturing semiconductor devices with titanium aluminum nitride work function 有权
标题翻译：制造具有钛氮化铝功能的半导体器件的方法
公开(公告)号：US06506676B2
公开(公告)日：2003-01-14
申请号：US10033509
申请日：2001-12-27
申请人： Dae Gyu Park , Tae Ho Cha , Se Aug Jang , Heung Jae Cho , Tae Kyun Kim , Kwan Yong Lim , In Seok Yeo , Jin Won Park
发明人： Dae Gyu Park , Tae Ho Cha , Se Aug Jang , Heung Jae Cho , Tae Kyun Kim , Kwan Yong Lim , In Seok Yeo , Jin Won Park
IPC分类号： H01L2144
CPC分类号： H01L21/28194 , C23C14/048 , C23C16/34 , H01L21/28556 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/518
摘要： A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.
摘要翻译：制造半导体器件的方法在制造金属栅极的过程中形成表面沟道CMOSFET。该方法在nMOS区域的栅极绝缘膜上形成具有约4.2至约4.3eV的功函数值的（TixAly）1-zNz膜（其中z范围为约0.0至约0.2），（TixAly）1 -zNz膜（其中z范围为约0.3至约0.6），在pMOS区域中的栅极绝缘膜上具有约4.8至约5.0eV的功函数值，从而在nMOS区域和 pMOS区域。因此，阈值电压降低。

2. 发明授权

US06537901B2 Method of manufacturing a transistor in a semiconductor device 失效
公开(公告)号：US06537901B2
公开(公告)日：2003-03-25
申请号：US09887511
申请日：2001-06-25
申请人： Tae Ho Cha , Se Aug Jang , Tae Kyun Kim , Dea Gyu Park , In Seok Yeo , Jin Won Park
发明人： Tae Ho Cha , Se Aug Jang , Tae Kyun Kim , Dea Gyu Park , In Seok Yeo , Jin Won Park
IPC分类号： H01L213205
CPC分类号： C23C16/34 , C23C14/0641 , H01L21/28079 , H01L21/28088 , H01L21/2855 , H01L21/28556 , H01L21/28562 , H01L21/28568 , H01L21/823828 , H01L29/4958 , H01L29/4966
摘要： There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45˜0.55, on a gate insulating film in a NMOS region, so that the work function becomes 4.0˜4.4 eV, and also forms a Ta film or a TaNx film at a high temperature or forms a second TaNx film in which the composition(x) of nitrogen is 0.6˜1.4 is formed, on a gate insulating film in a PMOS region, so that the work function becomes 4.8˜5.2 eV. Thus, the present invention can lower the threshold voltage by implementing a surface channel CMOS device both in the NMOS region and the PMOS region.

3. 发明授权

US06514827B2 Method for fabricating a dual metal gate for a semiconductor device 失效
标题翻译：半导体器件的双金属栅极的制造方法
公开(公告)号：US06514827B2
公开(公告)日：2003-02-04
申请号：US10034529
申请日：2001-12-28
申请人： Tae Kyun Kim , Se Aug Jang , Tae Ho Cha , In Seok Yeo
发明人： Tae Kyun Kim , Se Aug Jang , Tae Ho Cha , In Seok Yeo
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/823842
摘要： A method for fabricating a dual metal gate structure for a semiconductor device including deposition of a semiconductor substrate having PMOS and NMOS regions, a first gate having a first insulating layer and a first metal layer is formed in a first region. The first region is either the PMOS or NMOS region, and the remaining region becomes a second region. A dummy gate is formed in the second region. A spacer and a source/drain region are formed for each of the first and dummy gates. The dummy gate, however, is removed to expose a portion of the substrate in the second region. A second gate constructed of a second gate insulating layer and a second metal layer is then formed on the exposed portion of the substrate in the second region.
摘要翻译：一种用于制造半导体器件的双金属栅极结构的方法，包括具有PMOS和NMOS区域的半导体衬底的沉积，在第一区域中形成具有第一绝缘层和第一金属层的第一栅极。第一区域是PMOS或NMOS区域，其余区域成为第二区域。在第二区域中形成伪栅极。为第一和虚拟栅极中的每一个形成间隔物和源极/漏极区域。然而，去除伪栅极以暴露第二区域中的衬底的一部分。然后在第二区域中的衬底的暴露部分上形成由第二栅极绝缘层和第二金属层构成的第二栅极。

4. 发明授权

US06451639B1 Method for forming a gate in a semiconductor device 失效
标题翻译：在半导体器件中形成栅极的方法
公开(公告)号：US06451639B1
公开(公告)日：2002-09-17
申请号：US10036279
申请日：2001-11-07
申请人： Se Aug Jang , Tae Kyun Kim , Jae Young Kim , In Seok Yeo
发明人： Se Aug Jang , Tae Kyun Kim , Jae Young Kim , In Seok Yeo
IPC分类号： H01L21338
CPC分类号： H01L21/823842
摘要： A method of forming a semiconductor device gate including the steps of forming a dummy gate insulating layer on a semiconductor substrate having an isolating field oxide layer, successively depositing a dummy gate silicon layer and a hard mask layer on the dummy gate insulating layer, forming a hard mask layer and patterning the dummy gate silicon layer using the mask pattern as an etch barrier, forming a thermal oxide layer at both sidewalls of the dummy gate silicon layer by thermal oxidation on the resultant structure, forming spacers at both sidewalls of the dummy gate silicon layer, depositing an insulating interlayer on the resultant structure, polishing the insulating interlayer to expose the dummy gate silicon layer, forming a damascene structure by removing the dummy gate silicon and insulating layers, depositing a gate insulating layer and a gate metal layer on an entire surface of the semiconductor substrate having the damascene structure, and polishing the gate metal and insulating layers, thereby preventing the undercut at the bottom corners of a damascene groove.
摘要翻译：一种形成半导体器件栅极的方法，包括以下步骤：在具有隔离场氧化物层的半导体衬底上形成伪栅极绝缘层，在虚拟栅绝缘层上依次沉积伪栅极硅层和硬掩模层，形成硬掩模层，并且使用掩模图案作为蚀刻阻挡层来图案化伪栅极硅层，在所得结构上通过热氧化在所述伪栅极硅层的两个侧壁处形成热氧化物层，在所述伪栅极的两个侧壁处形成间隔物在所得到的结构上沉积绝缘中间层，抛光绝缘中间层以露出伪栅极硅层，通过去除伪栅极硅和绝缘层形成镶嵌结构，在栅极上沉积栅极绝缘层和栅极金属层半导体衬底的整个表面具有镶嵌结构，并且对栅极金属进行研磨从而防止镶嵌槽的底角处的底切。

5. 发明授权

US06255206B1 Method of forming gate electrode with titanium polycide structure 有权
标题翻译：用聚硅氧烷结构形成栅电极的方法
公开(公告)号：US06255206B1
公开(公告)日：2001-07-03
申请号：US09434647
申请日：1999-11-05
申请人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo , Sahng Kyoo Lee
发明人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo , Sahng Kyoo Lee
IPC分类号： H01L213205
CPC分类号： H01L21/28061 , H01L21/31683
摘要： A method of forming a gate electrode with a titanium polycide structure which can prevent abnormal oxidation of the gate electrode and reduce the resistivity of the gate electrode when performing a re-oxidation process, is disclosed. According to the present invention, a gate oxide layer, a polysilicon layer and a titanium silicide layer are formed on a semiconductor substrate, in sequence. A mask insulating layer is then formed in the shape of a gate electrode on the titanium silicide layer and the titanium silicide layer and the polysilicon layer are etched using the mask insulating layer to form a gate electrode. Thereafter, the substrate is oxidized using re-oxidation process to form an oxide layer with a uniform thickness on the side wall of the gate electrode and on the surface of the substrate. Here, the re-oxidation process is performed at the temperature of 750° C. or less using dry oxidation. Furthermore, the re-oxidation process is performed at the temperature of 700 to 750° C. and the oxide layer is formed to the thickness of 30 to 60 Å, preferably, about 50 Å.
摘要翻译：公开了一种形成具有可以防止栅电极的异常氧化并降低栅电极的电阻率的多晶硅化钛结构的栅电极的方法。根据本发明，栅极氧化物层在半导体衬底上依次形成多晶硅层和硅化钛层。然后在硅化钛层上形成栅极形状的掩模绝缘层，并且使用掩模绝缘层蚀刻钛硅化物层和多晶硅层以形成栅电极。此后，使用再氧化工艺氧化基板，在栅电极的侧壁和基板的表面上形成均匀厚度的氧化物层。这里，使用干式氧化在750℃以下的温度下进行再氧化处理。此外，再次氧化处理在700-750℃的温度下进行，氧化物层的厚度形成为30至60埃，优选为约50埃。

6. 发明授权

US08288819B2 Semiconductor device with bulb-type recessed channel and method for fabricating the same 有权
标题翻译：具有灯泡型凹槽的半导体器件及其制造方法
公开(公告)号：US08288819B2
公开(公告)日：2012-10-16
申请号：US12953255
申请日：2010-11-23
申请人： Yong Soo Kim , Hong Seon Yang , Se Aug Jang , Seung Ho Pyi , Kwon Hong , Heung Jae Cho , Kwan Yong Lim , Min Gyu Sung , Seung Ryong Lee , Tae Yoon Kim
发明人： Yong Soo Kim , Hong Seon Yang , Se Aug Jang , Seung Ho Pyi , Kwon Hong , Heung Jae Cho , Kwan Yong Lim , Min Gyu Sung , Seung Ryong Lee , Tae Yoon Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66553 , H01L27/10876 , H01L29/518 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.
摘要翻译：一种制造半导体器件的方法，包括提供具有灯泡型凹陷区域的衬底，在灯泡型凹陷区域上形成栅极绝缘层和衬底，并在栅极绝缘层上形成栅极导电层。栅极导电层填充灯泡型凹陷区域。栅极导电层包括两个或多个导电层和导电层之间的不连续界面。

7. 发明授权

US06436775B2 MOSFET device fabrication method capable of allowing application of self-aligned contact process while maintaining metal gate to have uniform thickness 有权
标题翻译： MOSFET器件制造方法能够允许施加自对准接触工艺，同时保持金属栅极具有均匀的厚度
公开(公告)号：US06436775B2
公开(公告)日：2002-08-20
申请号：US09884052
申请日：2001-06-20
申请人： Tae Kyun Kim , Se Aug Jang , In Seok Yeo
发明人： Tae Kyun Kim , Se Aug Jang , In Seok Yeo
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L21/31683 , H01L21/3212 , H01L29/66545
摘要： The MOSFET fabrication method allows application of a self-aligned contact (SAC) process while maintaining a metal gate, such as a tungsten gate, to have a uniform thickness. The process involves forming a metal oxide film during the formation of a metal gate structure of the MOSFET device. The metal oxide film is formed by subjecting the gate structure through a rapid thermal oxidation (RTO) treatment and then to an N2O plasma treatment. The treatments allow the thickness of the metal oxide to be precisely controlled. The metal oxide acts as an insulator, which prevents electrical shorts between the gate structure and a contact plug even if a misalignment of occurs during the SAC process. This is an improvement from the conventional practice of separately forming a SAC barrier film after the formation of the metal gate structure and thus saves money, time, and increases reliability and productivity. Also the performance characteristics of the device is enhanced.
摘要翻译： MOSFET制造方法允许在保持金属栅极（例如钨栅极）的同时具有均匀厚度的情况下应用自对准接触（SAC）工艺。该过程包括在形成MOSFET器件的金属栅极结构期间形成金属氧化物膜。金属氧化物膜通过对栅极结构进行快速热氧化（RTO）处理然后进行N 2 O等离子体处理而形成。这些处理使金属氧化物的厚度得到精确控制。金属氧化物充当绝缘体，即使在SAC工艺期间发生不对准，也可防止栅极结构和接触插塞之间的电短路。这是在形成金属栅极结构之后分开形成SAC阻挡膜的常规做法的改进，从而节省了金钱，时间，并提高了可靠性和生产率。此外，设备的性能特性也得到提高。

8. 发明授权

US06417055B2 Method for forming gate electrode for a semiconductor device 有权
标题翻译：用于形成半导体器件的栅电极的方法
公开(公告)号：US06417055B2
公开(公告)日：2002-07-09
申请号：US09895295
申请日：2001-07-02
申请人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo
发明人： Se Aug Jang , Tae Kyun Kim , In Seok Yeo
IPC分类号： H01L21336
CPC分类号： H01L21/76897 , H01L29/665
摘要： The present invention relates to a method for forming a gate electrode in a semiconductor device that is more tolerant of misalignment during contact formation processing. The improved gate structure reduces the formation of shorts between the gate electrode and subsequently formed conductors such as DRAM bit lines and storage lines. The gate electrode is formed from a damascene metal gate electrode having adjacent insulating spacers by partially etching the metal gate electrode to form a trench; depositing a nitride film; and etching the nitride film to form additional protective insulators above outer portions of the gate electrodes. With these protective insulators in place, subsequent contact processing becomes more tolerant of misalignment, reducing rework and improving yield.
摘要翻译：本发明涉及在接触形成处理中更容忍未对准的半导体器件中形成栅电极的方法。改进的栅极结构减少了栅电极和随后形成的导体（例如DRAM位线和存储线）之间的短路的形成。栅电极由具有相邻绝缘间隔物的镶嵌金属栅电极形成，部分蚀刻金属栅电极以形成沟槽; 沉积氮化物膜; 并蚀刻氮化物膜以在栅电极的外部部分上形成附加的保护绝缘体。通过这些保护绝缘子到位，随后的接触处理变得更加容忍不对准，减少返工和提高产量。

9. 发明授权

US06586288B2 Method of forming dual-metal gates in semiconductor device 有权
公开(公告)号：US06586288B2
公开(公告)日：2003-07-01
申请号：US09982841
申请日：2001-10-18
申请人： Tae Kyun Kim , Tae Ho Cha , Jeong Youb Lee , Se Aug Jang
发明人： Tae Kyun Kim , Tae Ho Cha , Jeong Youb Lee , Se Aug Jang
IPC分类号： H01L21338
CPC分类号： H01L21/823842 , H01L29/66545
摘要： A method of forming dual-metal gates in a semiconductor device, including the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area of the semiconductor substrate including the second groove, and forming a second metal gate in the second groove by etching the second metal layer and second gate insulating layer until the insulating interlayer is exposed.

10. 发明授权

US06468914B1 Method of forming gate electrode in semiconductor device 失效
标题翻译：在半导体器件中形成栅电极的方法
公开(公告)号：US06468914B1
公开(公告)日：2002-10-22
申请号：US09472541
申请日：1999-12-27
申请人： Se Aug Jang , In Seok Yeo
发明人： Se Aug Jang , In Seok Yeo
IPC分类号： H01L2144
CPC分类号： H01L29/6656 , H01L21/28061 , H01L21/28247 , H01L29/6659
摘要： A method of forming a gate electrode in a semiconductor device which can prevent abnormal oxidation of a titanium silicide layer when performing gate re-oxidation process after a gate electrode having a stacked structure of a doped polysilicon layer and the titanium silicide layer.
摘要翻译：一种在半导体器件中形成栅电极的方法，其可以在具有掺杂多晶硅层和硅化钛层的堆叠结构的栅极之后执行栅极再氧化处理时防止硅化钛层的异常氧化。

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