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1. 发明申请

US20110073841A1 NANO LINE STRUCTURES IN MICROELECTRONIC DEVICES 失效
标题翻译：微电子器件中的纳米线结构
公开(公告)号：US20110073841A1
公开(公告)日：2011-03-31
申请号：US12961883
申请日：2010-12-07
申请人： ZhongLiang Huo , Subramanya Mayya , Xiaofeng Wang , In-Seok Yeo
发明人： ZhongLiang Huo , Subramanya Mayya , Xiaofeng Wang , In-Seok Yeo
IPC分类号： H01L29/78 , H01L29/66 , B82Y99/00
CPC分类号： H01L51/0049 , B82Y10/00 , H01L29/0665 , H01L29/0673
摘要： A method of forming a microelectronic device includes forming a groove structure having opposing sidewalls and a surface therebetween on a substrate to define a nano line arrangement region. The nano line arrangement region has a predetermined width and a predetermined length greater than the width. At least one nano line is formed in the nano line arrangement region extending substantially along the length thereof and coupled to the surface of the groove structure to define a nano line structure. Related devices are also discussed.
摘要翻译：形成微电子器件的方法包括在衬底上形成具有相对侧壁及其表面的沟槽结构，以限定纳米线布置区域。纳米线排列区域具有预定宽度和大于宽度的预定长度。在纳米线布置区域中形成至少一条纳米线，其基本上沿着其长度延伸并耦合到凹槽结构的表面以限定纳米线结构。还讨论了相关设备。

2. 发明授权

US07915668B2 Semiconductor device and method for forming the same 失效
标题翻译：半导体装置及其形成方法
公开(公告)号：US07915668B2
公开(公告)日：2011-03-29
申请号：US11700019
申请日：2007-01-31
申请人： Subramanya Mayya Kolake , In-Seok Yeo , Kyong-Hee Joo
发明人： Subramanya Mayya Kolake , In-Seok Yeo , Kyong-Hee Joo
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L51/0512 , B82Y10/00 , H01L29/42332 , H01L51/0046 , H01L51/0075
摘要： A memory device includes an insulating layer formed over a substrate, a gate formed over the insulating layer, and charge storage elements disposed over the insulating layer. The charge storage elements are separated from each other and are electrically insulated, and each of the charge storage elements is capable of storing at least one charge. The charge storage elements can include fullerenes.
摘要翻译：存储器件包括形成在衬底上的绝缘层，形成在绝缘层上的栅极和设置在绝缘层上的电荷存储元件。电荷存储元件彼此分离并且电绝缘，并且每个电荷存储元件能够存储至少一个电荷。电荷存储元件可以包括富勒烯。

3. 发明授权

US07875920B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07875920B2
公开(公告)日：2011-01-25
申请号：US12805686
申请日：2010-08-13
申请人： Young-moon Choi , Ji-young Kim , In-seok Yeo , Sun-woo Lee
发明人： Young-moon Choi , Ji-young Kim , In-seok Yeo , Sun-woo Lee
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , B82Y10/00 , H01L27/10817 , H01L27/10852 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/41725 , Y10S977/742 , Y10S977/762 , Y10S977/766
摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes or wires on a semiconductor substrate, a dielectric layer on the surface of the lower electrode, and an upper electrode on the surface of the dielectric layer, wherein the plurality of tubes or wires radiate outwardly from each other centering on the lower portion of the plurality of tubes or wires. Thus, the off current of the capacitor may be increased by increasing the surface area of the lower electrodes of the capacitor.
摘要翻译：提供半导体器件和制造半导体器件的方法，例如，使用碳纳米管或纳米线作为电容器的下电极的半导体器件，以及制造半导体器件的方法。半导体器件可以包括在半导体衬底上包括多个管或导线的下电极，下电极表面上的电介质层和介电层表面上的上电极，其中多个管或电线以多个管或线的下部为中心彼此向外辐射。因此，可以通过增加电容器的下电极的表面积来增加电容器的截止电流。

4. 发明申请

US20100308388A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100308388A1
公开(公告)日：2010-12-09
申请号：US12805686
申请日：2010-08-13
申请人： Young-moon Choi , Ji-young Kim , In-seok Yeo , Sun-woo Lee
发明人： Young-moon Choi , Ji-young Kim , In-seok Yeo , Sun-woo Lee
IPC分类号： H01L29/94
CPC分类号： H01L28/91 , B82Y10/00 , H01L27/10817 , H01L27/10852 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/41725 , Y10S977/742 , Y10S977/762 , Y10S977/766
摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes or wires on a semiconductor substrate, a dielectric layer on the surface of the lower electrode, and an upper electrode on the surface of the dielectric layer, wherein the plurality of tubes or wires radiate outwardly from each other centering on the lower portion of the plurality of tubes or wires. Thus, the off current of the capacitor may be increased by increasing the surface area of the lower electrodes of the capacitor.
摘要翻译：提供半导体器件和制造半导体器件的方法，例如，使用碳纳米管或纳米线作为电容器的下电极的半导体器件，以及制造半导体器件的方法。半导体器件可以包括在半导体衬底上包括多个管或导线的下电极，下电极表面上的电介质层和介电层表面上的上电极，其中多个管或电线以多个管或线的下部为中心彼此向外辐射。因此，可以通过增加电容器的下电极的表面积来增加电容器的截止电流。

5. 发明授权

US07799633B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07799633B2
公开(公告)日：2010-09-21
申请号：US11980355
申请日：2007-10-31
申请人： Young-moon Choi , Ji-young Kim , In-seok Yeo , Sun-woo Lee
发明人： Young-moon Choi , Ji-young Kim , In-seok Yeo , Sun-woo Lee
IPC分类号： H01L21/8242 , H01L27/108
CPC分类号： H01L28/91 , B82Y10/00 , H01L27/10817 , H01L27/10852 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/41725 , Y10S977/742 , Y10S977/762 , Y10S977/766
摘要： Provided are a semiconductor device and a method of manufacturing the semiconductor device, for example, a semiconductor device using carbon nanotubes or nanowires as lower electrodes of a capacitor, and a method of manufacturing the semiconductor device. The semiconductor device may include a lower electrode including a plurality of tubes or wires on a semiconductor substrate, a dielectric layer on the surface of the lower electrode, and an upper electrode on the surface of the dielectric layer, wherein the plurality of tubes or wires radiate outwardly from each other centering on the lower portion of the plurality of tubes or wires. Thus, the off current of the capacitor may be increased by increasing the surface area of the lower electrodes of the capacitor.
摘要翻译：提供半导体器件和制造半导体器件的方法，例如，使用碳纳米管或纳米线作为电容器的下电极的半导体器件，以及制造半导体器件的方法。半导体器件可以包括在半导体衬底上包括多个管或导线的下电极，下电极表面上的电介质层和介电层表面上的上电极，其中多个管或电线以多个管或线的下部为中心彼此向外辐射。因此，可以通过增加电容器的下电极的表面积来增加电容器的截止电流。

6. 发明授权

US07528042B2 Method for fabricating semiconductor devices having dual gate oxide layer 有权
标题翻译：制造具有双栅氧化层的半导体器件的方法
公开(公告)号：US07528042B2
公开(公告)日：2009-05-05
申请号：US11477090
申请日：2006-06-28
申请人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
发明人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/2236 , H01L21/28202 , H01L21/3144 , H01L21/823481 , H01L29/518
摘要： A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.
摘要翻译：一种形成双栅极氧化层的方法，包括以下步骤：a）在半导体衬底上形成栅极氧化层; 和b）通过执行去耦等离子体处理来增加栅极氧化物层的一部分的厚度。额外的热处理不是必需的，因为双栅极氧化物层由解耦的等离子体形成。此外，由于硅衬底没有被损坏，所以可以确保半导体器件的沟道特性。此外，由于在没有额外的沟道离子注入的情况下单元区域中的阈值电压增加，所以可以提高半导体器件的电特性。

7. 发明申请

US20080246078A1 Charge trap flash memory device and memory card and system including the same 有权
标题翻译：充电陷阱闪存设备和存储卡及系统包括相同
公开(公告)号：US20080246078A1
公开(公告)日：2008-10-09
申请号：US12080315
申请日：2008-04-02
申请人： Zong-liang Huo , In-seok Yeo , Seung-Hyun Lim , Kyong-hee Joo , Jun-kyu Yang
发明人： Zong-liang Huo , In-seok Yeo , Seung-Hyun Lim , Kyong-hee Joo , Jun-kyu Yang
IPC分类号： H01L29/792
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42332 , H01L29/7881
摘要： A charge trap flash memory device and method of making same are provided. The device includes: a tunnel insulating layer, a charge trap layer; a blocking insulating layer; and a gate electrode sequentially formed on a substrate. The charge trap layer includes: plural trap layers comprising a first material having a first band gap energy level; spaced apart nanodots, each nanodot being at least partially surrounded by at least one of the trap layers, wherein the nanodots comprise a second material having a second band gap energy level that is lower than the first band gap energy level; and an intermediate blocking layer comprising a third material having a third band gap energy level that is higher than the first band gap energy level, formed between at least two of the trap layers. This structure prevents loss of charges from the charge trap layer and improves charge storage capacity.
摘要翻译：提供了一种电荷阱闪存器件及其制造方法。该器件包括：隧道绝缘层，电荷陷阱层; 阻挡绝缘层; 以及依次形成在基板上的栅电极。电荷陷阱层包括：多个陷阱层，包括具有第一带隙能级的第一材料; 间隔开的纳米点，每个纳米点至少部分地被至少一个捕获层包围，其中该纳米点包括具有低于第一带隙能级的第二带隙能级的第二材料; 以及中间阻挡层，其包括形成在至少两个捕获层之间的具有高于第一带隙能级的第三带隙能级的第三材料。这种结构防止电荷陷阱层的电荷损失并且改善电荷存储容量。

8. 发明授权

US07157339B2 Method for fabricating semiconductor devices having dual gate oxide layers 有权
标题翻译：制造具有双栅氧化层的半导体器件的方法
公开(公告)号：US07157339B2
公开(公告)日：2007-01-02
申请号：US10292296
申请日：2002-11-12
申请人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
发明人： Kwan-Yong Lim , Heung-Jae Cho , Dae-Gyu Park , Tae-Ho Cha , In-Seok Yeo
IPC分类号： H01L21/336
CPC分类号： H01L21/823462 , H01L21/2236 , H01L21/28202 , H01L21/3144 , H01L21/823481 , H01L29/518
摘要： A method for forming a dual gate oxide layer, including the steps of: a) forming a gate oxide layer on a semiconductor substrate; and b) increasing a thickness of a part of the gate oxide layer by performing a decoupled plasma treatment. Additional heat processes are not necessary because the dual gate oxide layer is formed with the decoupled plasma. Also, the channel characteristic of the semiconductor device can be ensured because the silicon substrate is not damaged. Furthermore, because the threshold voltage in the cell region is increased without additional channel ion implantation, the electrical characteristic of the semiconductor device can be enhanced.
摘要翻译：一种形成双栅极氧化层的方法，包括以下步骤：a）在半导体衬底上形成栅极氧化层; 和b）通过执行去耦等离子体处理来增加栅极氧化物层的一部分的厚度。额外的热处理不是必需的，因为双栅极氧化物层由解耦的等离子体形成。此外，由于硅基板没有被损坏，所以可以确保半导体器件的沟道特性。此外，由于在没有额外的沟道离子注入的情况下单元区域中的阈值电压增加，所以可以提高半导体器件的电特性。

9. 发明申请

US20060249770A1 Single Transistor Floating-Body DRAM Devices Having Vertical Channel Transistor Structures and Methods of Fabricating the Same 失效
标题翻译：具有垂直沟道晶体管结构的单晶体管浮动体DRAM器件及其制造方法
公开(公告)号：US20060249770A1
公开(公告)日：2006-11-09
申请号：US11380946
申请日：2006-05-01
申请人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
发明人： Zong-Liang Huo , Seung-Jae Baik , In-Seok Yeo , Hong-Sik Yoon , Shi-Eun Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/108 , H01L21/84 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： Single transistor floating-body DRAM devices have a vertical channel transistor structure. The DRAM devices include a substrate, and first and second floating bodies disposed on the substrate and isolated from each other. A source region and a drain region are disposed under and above each of the first and second floating bodies. A gate electrode is disposed between the first and second floating bodies. Methods of fabricating the single transistor floating-body DRAM devices are also provided.
摘要翻译：单晶体体浮体DRAM器件具有垂直沟道晶体管结构。 DRAM器件包括衬底，以及设置在衬底上并彼此隔离的第一和第二浮体。源极区域和漏极区域设置在第一和第二浮体的每一个之下和之上。栅电极设置在第一和第二浮体之间。还提供了制造单晶体管浮体DRAM器件的方法。

10. 发明授权

US06537901B2 Method of manufacturing a transistor in a semiconductor device 失效
公开(公告)号：US06537901B2
公开(公告)日：2003-03-25
申请号：US09887511
申请日：2001-06-25
申请人： Tae Ho Cha , Se Aug Jang , Tae Kyun Kim , Dea Gyu Park , In Seok Yeo , Jin Won Park
发明人： Tae Ho Cha , Se Aug Jang , Tae Kyun Kim , Dea Gyu Park , In Seok Yeo , Jin Won Park
IPC分类号： H01L213205
CPC分类号： C23C16/34 , C23C14/0641 , H01L21/28079 , H01L21/28088 , H01L21/2855 , H01L21/28556 , H01L21/28562 , H01L21/28568 , H01L21/823828 , H01L29/4958 , H01L29/4966
摘要： There is disclosed a method of manufacturing a transistor in a semiconductor device. The present invention forms a Ta film or a TaNx film at a low temperature or forms a first TaNx film in which the composition(x) of nitrogen is 0.45˜0.55, on a gate insulating film in a NMOS region, so that the work function becomes 4.0˜4.4 eV, and also forms a Ta film or a TaNx film at a high temperature or forms a second TaNx film in which the composition(x) of nitrogen is 0.6˜1.4 is formed, on a gate insulating film in a PMOS region, so that the work function becomes 4.8˜5.2 eV. Thus, the present invention can lower the threshold voltage by implementing a surface channel CMOS device both in the NMOS region and the PMOS region.

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