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1. 发明授权

US08288819B2 Semiconductor device with bulb-type recessed channel and method for fabricating the same 有权
标题翻译：具有灯泡型凹槽的半导体器件及其制造方法
公开(公告)号：US08288819B2
公开(公告)日：2012-10-16
申请号：US12953255
申请日：2010-11-23
申请人： Yong Soo Kim , Hong Seon Yang , Se Aug Jang , Seung Ho Pyi , Kwon Hong , Heung Jae Cho , Kwan Yong Lim , Min Gyu Sung , Seung Ryong Lee , Tae Yoon Kim
发明人： Yong Soo Kim , Hong Seon Yang , Se Aug Jang , Seung Ho Pyi , Kwon Hong , Heung Jae Cho , Kwan Yong Lim , Min Gyu Sung , Seung Ryong Lee , Tae Yoon Kim
IPC分类号： H01L21/336
CPC分类号： H01L29/66553 , H01L27/10876 , H01L29/518 , H01L29/66621
摘要： A method for fabricating a semiconductor device includes providing a substrate having a bulb-type recessed region, forming a gate insulating layer over the bulb-type recessed region and the substrate, and forming a gate conductive layer over the gate insulating layer. The gate conductive layer fills the bulb-type recessed region. The gate conductive layer includes two or more conductive layers and a discontinuous interface between the conductive layers.
摘要翻译：一种制造半导体器件的方法，包括提供具有灯泡型凹陷区域的衬底，在灯泡型凹陷区域上形成栅极绝缘层和衬底，并在栅极绝缘层上形成栅极导电层。栅极导电层填充灯泡型凹陷区域。栅极导电层包括两个或多个导电层和导电层之间的不连续界面。

2. 发明授权

US06506676B2 Method of manufacturing semiconductor devices with titanium aluminum nitride work function 有权
标题翻译：制造具有钛氮化铝功能的半导体器件的方法
公开(公告)号：US06506676B2
公开(公告)日：2003-01-14
申请号：US10033509
申请日：2001-12-27
申请人： Dae Gyu Park , Tae Ho Cha , Se Aug Jang , Heung Jae Cho , Tae Kyun Kim , Kwan Yong Lim , In Seok Yeo , Jin Won Park
发明人： Dae Gyu Park , Tae Ho Cha , Se Aug Jang , Heung Jae Cho , Tae Kyun Kim , Kwan Yong Lim , In Seok Yeo , Jin Won Park
IPC分类号： H01L2144
CPC分类号： H01L21/28194 , C23C14/048 , C23C16/34 , H01L21/28556 , H01L21/823842 , H01L29/4966 , H01L29/513 , H01L29/518
摘要： A method of manufacturing semiconductor devices forms a surface channel CMOSFET in the process of manufacturing a metal gate. The method forms a (TixAly)1-zNz film (where z ranges from about 0.0 to about 0.2) having a work function value ranging from about 4.2 to about 4.3 eV on a gate insulating film in a nMOS region, a (TixAly)1-zNz film (where z ranges from about 0.3 to about 0.6) having a work function value ranging from about 4.8 to about 5.0 eV on the gate insulating film in a pMOS region, thus implementing a surface channel CMOS device both in the nMOS region and the pMOS region. Therefore, the threshold voltage is reduced.
摘要翻译：制造半导体器件的方法在制造金属栅极的过程中形成表面沟道CMOSFET。该方法在nMOS区域的栅极绝缘膜上形成具有约4.2至约4.3eV的功函数值的（TixAly）1-zNz膜（其中z范围为约0.0至约0.2），（TixAly）1 -zNz膜（其中z范围为约0.3至约0.6），在pMOS区域中的栅极绝缘膜上具有约4.8至约5.0eV的功函数值，从而在nMOS区域和 pMOS区域。因此，阈值电压降低。

3. 发明授权

US07981786B2 Method of fabricating non-volatile memory device having charge trapping layer 失效
标题翻译：制造具有电荷捕获层的非易失性存储器件的方法
公开(公告)号：US07981786B2
公开(公告)日：2011-07-19
申请号：US11966231
申请日：2007-12-28
申请人： Moon Sig Joo , Seung Ho Pyi , Ki Seon Park , Heung Jae Cho , Yong Top Kim
发明人： Moon Sig Joo , Seung Ho Pyi , Ki Seon Park , Heung Jae Cho , Yong Top Kim
IPC分类号： H01L21/3205 , H01L21/4763 , H01L21/302 , H01L21/461
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , Y10S438/942
摘要： A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.
摘要翻译：一种制造具有电荷捕获层的非易失性存储器件的方法包括在衬底上形成隧道层，电荷俘获层，阻挡层和控制栅电极层，在控制栅电极层上形成掩模层图案使用掩模层图案作为蚀刻掩模进行蚀刻处理以去除控制栅电极层的暴露部分，其中蚀刻工艺作为过度蚀刻进行，以将电荷捕获层除去指定厚度，形成绝缘层用于阻止电荷在控制栅电极层和掩模层图案上移动，对绝缘层进行各向异性蚀刻，以在控制栅电极层的侧壁和阻挡层的一部分上侧壁上形成绝缘层图案，以及对通过各向异性蚀刻暴露的阻挡层进行蚀刻处理，其中执行蚀刻处理作为过量蚀刻以将电荷捕获层除去指定的厚度。

4. 发明授权

US06248632B1 Method of forming gate electrode with polycide structure in semiconductor device 有权
标题翻译：在半导体器件中形成具有聚硅氧烷结构的栅电极的方法
公开(公告)号：US06248632B1
公开(公告)日：2001-06-19
申请号：US09459510
申请日：1999-12-13
申请人： Se Aug Jang , Heung Jae Cho
发明人： Se Aug Jang , Heung Jae Cho
IPC分类号： H01L21336
CPC分类号： H01L29/4941 , H01L21/28052
摘要： A method of forming a gate electrode with a polycide structure in a semiconductor device which can improve the interface roughness between a polysilicon layer and a silicon layer, is disclosed. According to the present invention, a gate insulating layer and a doped polysilicon layer on the gate insulating layer are formed on a semiconductor substrate. A nitrogenous polysilicon layer is then formed on the surface of the polysilicon layer by ion-implanting nitrogen ions (N2+) into the surface of the polysilicon layer or by thermal-treating the surface of the polysilicon under the atmosphere of gas containing nitrogen. Next, a metal silicide layer is formed on the nitrogenous polysilicon layer. Thereafter, the metal silicide layer, the nitrogenous polysilicon layer and the polysilicon layer are etched sequentially to form a gate electrode.
摘要翻译：公开了一种在可以改善多晶硅层和硅层之间的界面粗糙度的半导体器件中形成具有聚硅氧烷结构的栅电极的方法。根据本发明，在半导体衬底上形成栅绝缘层上的栅绝缘层和掺杂多晶硅层。然后通过将氮离子（N 2 +）离子注入到多晶硅层的表面中或通过在含氮气体的气氛下热处理多晶硅的表面，在多晶硅层的表面上形成含氮多晶硅层。接着，在氮多晶硅层上形成金属硅化物层。此后，依次蚀刻金属硅化物层，氮多晶硅层和多晶硅层以形成栅电极。

5. 发明申请

US20090004802A1 METHOD OF FABRICATING NON-VOLATILE MEMORY DEVICE HAVING CHARGE TRAPPING LAYER 失效
标题翻译：制造具有电荷捕获层的非易失性存储器件的方法
公开(公告)号：US20090004802A1
公开(公告)日：2009-01-01
申请号：US11966231
申请日：2007-12-28
申请人： Moon Sig Joo , Seung Ho Pyi , Ki Seon Park , Heung Jae Cho , Yong Top Kim
发明人： Moon Sig Joo , Seung Ho Pyi , Ki Seon Park , Heung Jae Cho , Yong Top Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L21/28282 , H01L27/115 , Y10S438/942
摘要： A method of fabricating a non-volatile memory device having a charge trapping layer includes forming a tunneling layer, a charge trapping layer, a blocking layer and a control gate electrode layer over a substrate, forming a mask layer pattern on the control gate electrode layer, performing an etching process using the mask layer pattern as an etching mask to remove an exposed portion of the control gate electrode layer, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness, forming an insulating layer for blocking charges from moving on the control gate electrode layer and the mask layer pattern, performing anisotropic etching on the insulating layer to form an insulating layer pattern on a sidewall of the control gate electrode layer and a partial upper sidewall of the blocking layer, and performing an etching process on the blocking layer exposed by the anisotropic etching, wherein the etching process is performed as excessive etching to remove the charge trapping layer by a specified thickness.
摘要翻译：一种制造具有电荷捕获层的非易失性存储器件的方法包括在衬底上形成隧道层，电荷俘获层，阻挡层和控制栅电极层，在控制栅电极层上形成掩模层图案使用掩模层图案作为蚀刻掩模进行蚀刻处理以去除控制栅电极层的暴露部分，其中蚀刻工艺作为过度蚀刻进行，以将电荷捕获层除去指定厚度，形成绝缘层用于阻止电荷在控制栅电极层和掩模层图案上移动，对绝缘层进行各向异性蚀刻，以在控制栅电极层的侧壁和阻挡层的一部分上侧壁上形成绝缘层图案，以及对通过各向异性蚀刻暴露的阻挡层进行蚀刻处理，其中执行蚀刻处理作为过量蚀刻以将电荷捕获层除去指定的厚度。

6. 发明授权

US07081390B2 Semiconductor device and a method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07081390B2
公开(公告)日：2006-07-25
申请号：US10614189
申请日：2003-07-08
申请人： Kwan Yong Lim , Heung Jae Cho , Jung Ho Lee
发明人： Kwan Yong Lim , Heung Jae Cho , Jung Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66651 , H01L21/28123
摘要： Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate pre-cleaning process. It is thus possible to prevent formation of a moat at the top corners of the device isolation film and the gate oxide film from being thinly formed, thereby improving reliability and electrical characteristics of the device.
摘要翻译：公开了半导体器件及其制造方法。使用具有与氮化物或氧化物不同的蚀刻选择比的材料并且在氧化物栅极预清洁工艺中不被蚀刻的材料在器件隔离膜的顶角形成防蚀刻膜。因此，可以防止在器件隔离膜和栅极氧化膜的顶角形成护城河，从而提高器件的可靠性和电气特性。

7. 发明授权

US07157359B2 Method of forming a metal gate in a semiconductor device using atomic layer deposition process 有权
标题翻译：使用原子层沉积工艺在半导体器件中形成金属栅极的方法
公开(公告)号：US07157359B2
公开(公告)日：2007-01-02
申请号：US10036156
申请日：2001-12-26
申请人： Dae Gyu Park , Heung Jae Cho , Kwan Yong Lim
发明人： Dae Gyu Park , Heung Jae Cho , Kwan Yong Lim
IPC分类号： H01L21/3205
CPC分类号： H01L29/4966 , H01L21/28088
摘要： A method for forming a metal gate capable of preventing degradation in a characteristic of a gate insulating film upon formation of the metal gate. The method of forming the metal gate comprises the steps of providing a silicon substrate having device isolation films of a trench shape for defining an active region; forming a gate insulating film on the surface of the silicon substrate by means of a thermal oxidization process; sequentially forming a barrier metal film and a metal film for the gate on the gate insulating film; and patterning the metal film for the gate, the barrier metal film and the gate insulating film, wherein deposition of the barrier metal film and the metal film for the gate is performed by means of an atomic layer deposition (ALD) process or remote plasma chemical vapor deposition (CVD) process.
摘要翻译：一种用于形成金属栅极的方法，其能够防止在形成金属栅极时栅极绝缘膜的特性劣化。形成金属栅极的方法包括以下步骤：提供具有用于限定有源区的沟槽形状的器件隔离膜的硅衬底; 通过热氧化工艺在硅衬底的表面上形成栅极绝缘膜; 在栅极绝缘膜上依次形成阻挡金属膜和栅极用金属膜; 并且对栅极金属膜，阻挡金属膜和栅极绝缘膜进行图案化，其中通过原子层沉积（ALD）工艺或远程等离子体化学技术进行用于栅极的阻挡金属膜和金属膜的沉积气相沉积（CVD）工艺。

8. 发明授权

US06987056B2 Method of forming gates in semiconductor devices 失效
标题翻译：在半导体器件中形成栅极的方法
公开(公告)号：US06987056B2
公开(公告)日：2006-01-17
申请号：US10615478
申请日：2003-07-08
申请人： Kwan Yong Lim , Heung Jae Cho , Tae Hang Ahn
发明人： Kwan Yong Lim , Heung Jae Cho , Tae Hang Ahn
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/02318 , H01L21/02183 , H01L21/02238 , H01L21/02244 , H01L21/02252 , H01L21/31658 , H01L21/31662 , H01L29/4941 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66477
摘要： Disclosed is the method of forming the gate in the semiconductor device. The present method can prevent abnormal oxidization and lifting at the interface of the stack gate consisting of polysilicon and a metal and can be applied to even the single metal gate, by replacing a re-oxidization process for recovering damage of the gate oxide film generated in the gate patterning process with the oxygen plasma treatment.
摘要翻译：公开了在半导体器件中形成栅极的方法。本方法可以防止在由多晶硅和金属构成的堆叠栅极的界面处的异常氧化和提升，并且可以应用于甚至单个金属栅极，通过替换用于恢复在...中产生的栅极氧化膜的损伤的再氧化过程采用氧等离子体处理的栅极图案化工艺。

9. 发明授权

US06828185B2 CMOS of semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件的CMOS及其制造方法
公开(公告)号：US06828185B2
公开(公告)日：2004-12-07
申请号：US10230345
申请日：2002-08-29
申请人： Kwan Yong Lim , Heung Jae Cho , Dae Gyu Park , In Seok Yeo
发明人： Kwan Yong Lim , Heung Jae Cho , Dae Gyu Park , In Seok Yeo
IPC分类号： H01L218238
CPC分类号： H01L21/823857
摘要： The present invention discloses the single gate CMOS with the surface channel manufactured according to the manufacturing method of the present invention is very advantageous for improving the characteristics, yield and reliability of the device, by performing decoupled plasma nitridation (DPN) process on the gate oxide film of the cell NMOS and the peripheral PMOS, respectively, thereby forming a silicon nitride on the surface of the gate oxide film. Further, the single gate CMOS with the surface channel can be formed more easily through the simplified process in overall, without requiring a separate transient ion implantation process, even when the gate electrode of the n+ polysilicon layer is used, by having the threshold voltage of the cell NMOS be approximately +0.9V, the threshold voltage of the peripheral PMOS be approximately −0.5V and above, and the threshold voltage of the peripheral NMOS be approximately +0.5V and below. In addition, since the cell NMOS already has +0.9V of threshold voltage, back bias does not have to be applied separately to achieve the +0.9V threshold voltage, and the device with low power consumption is formed successfully.
摘要翻译：本发明公开了根据本发明的制造方法制造的具有表面通道的单栅极CMOS通过在栅极氧化物上进行去耦等离子体氮化（DPN）工艺来改善器件的特性，产量和可靠性是非常有利的电池NMOS和外围PMOS的膜，从而在栅极氧化膜的表面上形成氮化硅。此外，即使当使用n +多晶硅层的栅电极时，也可以通过整体的简化处理更容易地形成具有表面通道的单栅极CMOS，而不需要单独的瞬态离子注入工艺，单元NMOS的阈值电压约为+ 0.9V，外围PMOS的阈值电压约为-0.5V及以上，并且外围NMOS的阈值电压约为+ 0.5V及以下。另外，由于单元NMOS已经具有阈值电压的+ 0.9V，所以不必单独施加反向偏置以实现+ 0.9V阈值电压，并且成功地形成具有低功耗的器件。

10. 发明授权

US07271066B2 Semiconductor device and a method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US07271066B2
公开(公告)日：2007-09-18
申请号：US11086286
申请日：2005-03-23
申请人： Kwan Yong Lim , Heung Jae Cho , Jung Ho Lee
发明人： Kwan Yong Lim , Heung Jae Cho , Jung Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/66651 , H01L21/28123
摘要： Disclosed are a semiconductor devices and method of fabricating the same. Anti-etch films are formed in the top corners of the device isolation film using a material that has a different etch selectivity ratio from nitride or oxide and is not etched in an oxide gate pre-cleaning process. It is thus possible to prevent formation of a moat at the top corners of the device isolation film and the gate oxide film from being thinly formed, thereby improving reliability and electrical characteristics of the device.
摘要翻译：公开了半导体器件及其制造方法。使用具有与氮化物或氧化物不同的蚀刻选择比的材料并且在氧化物栅极预清洁工艺中不被蚀刻的材料在器件隔离膜的顶角形成防蚀刻膜。因此，可以防止在器件隔离膜和栅极氧化膜的顶角形成护城河，从而提高器件的可靠性和电气特性。

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