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1. 发明授权

US5059815A High voltage charge pumps with series capacitors 失效
标题翻译：具有串联电容器的高压充电泵
公开(公告)号：US5059815A
公开(公告)日：1991-10-22
申请号：US505335
申请日：1990-04-05
申请人： Colin S. Bill , Michael A. Van Buskirk , Antonio J. Montalvo
发明人： Colin S. Bill , Michael A. Van Buskirk , Antonio J. Montalvo
IPC分类号： H02M3/07 , G05F3/20 , H01L27/02
CPC分类号： G05F3/205 , H01L27/0222
摘要： A charge pump circuit is provided comprising a MOS capacitor, a capacitor ("series capacitor") connected in series, a MOSFET diode, and a voltage clamp connected to the common node of the MOS capacitor and the series capacitor. A number of these charge pump circuits may be cascaded to form a multi-stage charge pump circuit. Each charge pump circuit may attain output voltage higher than the oxide breakdown voltage of each individual MOS capacitor. This charge pump circuit can also operate under low voltage power supply conditions.

2. 发明授权

US5126808A Flash EEPROM array with paged erase architecture 失效
标题翻译：具有分页擦除架构的闪存EEPROM阵列
公开(公告)号：US5126808A
公开(公告)日：1992-06-30
申请号：US426601
申请日：1989-10-23
申请人： Antonio J. Montalvo , Michael A. Van Buskirk
发明人： Antonio J. Montalvo , Michael A. Van Buskirk
IPC分类号： G11C16/16 , H01L29/788
CPC分类号： H01L29/7885 , G11C16/16
摘要： A flash EEPROM array architecture including a plurality of pages is provided according to the principles of this invention. Each page of the array is isolated from other pages in the array during reading, programming and erasing of the page. The novel architecture of this invention includes means for erasing through the gate of the flash EEPROM cell.
摘要翻译：根据本发明的原理提供了包括多页的快闪EEPROM阵列架构。在读取，编程和擦除页面时，阵列的每一页与阵列中的其他页面隔离。本发明的新颖结构包括用于擦除闪存EEPROM单元的栅极的装置。

3. 发明授权

US07474579B2 Use of periodic refresh in medium retention memory arrays 有权
标题翻译：在介质保留存储器阵列中使用定期更新
公开(公告)号：US07474579B2
公开(公告)日：2009-01-06
申请号：US11613832
申请日：2006-12-20
申请人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
发明人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C13/0033 , G11C13/0069 , G11C16/3431
摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
摘要翻译：公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法跟踪元件的电阻已达到或超过预定参考阈值电阻值。跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

4. 发明申请

US20080151669A1 USE OF PERIODIC REFRESH IN MEDIUM RETENTION MEMORY ARRAYS 有权
标题翻译：在中继记忆阵列中使用周期性刷新
公开(公告)号：US20080151669A1
公开(公告)日：2008-06-26
申请号：US11613832
申请日：2006-12-20
申请人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
发明人： Colin S. Bill , Swaroop Kaza , Wei Daisy Cai , Tzu-Ning Fang , David Gaun , Eugen Gershon , Michael A. Van Buskirk , Jean Wu
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/40615 , G11C13/0033 , G11C13/0069 , G11C16/3431
摘要： Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
摘要翻译：公开了通过评估与存储器阵列相关联的跟踪元件中的电阻水平并在确定存储器阵列的情况下刷新存储器阵列时有助于在诸如纳米级电阻存储器单元阵列之类的数据保持装置中扩展数据保留时间的系统和方法跟踪元件的电阻已达到或超过预定参考阈值电阻值。跟踪元件可以是阵列本身内的存储器单元，并且可以具有基本上高于阵列中的编程存储器单元的初始电阻值的初始电阻值，使得跟踪单元中的电阻增加将导致跟踪单元在核心存储器单元中发生数据损坏/丢失之前达到阈值并触发阵列刷新。

5. 发明申请

US20140003125A1 Resistive Devices and Methods of Operation Thereof 有权
标题翻译：电阻器件及其操作方法
公开(公告)号：US20140003125A1
公开(公告)日：2014-01-02
申请号：US13610690
申请日：2012-09-11
申请人： Foroozan Sarah Koushan , Michael A. Van Buskirk
发明人： Foroozan Sarah Koushan , Michael A. Van Buskirk
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0009 , G11C13/0011 , G11C13/004 , G11C13/0069 , G11C2013/0071 , G11C2013/0092 , G11C2213/74 , G11C2213/79
摘要： In accordance with an embodiment of the present invention, a method of operating a resistive switching device includes applying a signal including a pulse on a first access terminal of an access device having the first access terminal and a second access terminal. The second access terminal is coupled to a first terminal of a two terminal resistive switching device. The resistive switching device has the first terminal and a second terminal. The resistive switching device has a first state and a second state. The pulse includes a first ramp from a first voltage to a second voltage over a first time period, a second ramp from the second voltage to a third voltage over a second time period, and a third ramp from the third voltage to a fourth voltage over a third time period. The second ramp and the third ramp have an opposite slope to the first ramp. The sum of the first time period and the second time period is less than the third time period.
摘要翻译：根据本发明的实施例，一种操作电阻式交换设备的方法包括：在具有第一接入终端的接入设备的第一接入终端和第二接入终端上应用包括脉冲的信号。第二接入终端耦合到两端电阻式交换设备的第一终端。电阻式开关装置具有第一端子和第二端子。电阻式开关装置具有第一状态和第二状态。脉冲包括在第一时间段内从第一电压到第二电压的第一斜坡，在第二时间段内从第二电压到第三电压的第二斜坡，以及从第三电压到第四电压的第三斜坡第三个时期。第二斜坡和第三斜坡与第一坡道具有相反的斜坡。第一时间段和第二时间段的总和小于第三时间段。

6. 发明授权

US08547738B2 Techniques for providing a semiconductor memory device 有权
标题翻译：提供半导体存储器件的技术
公开(公告)号：US08547738B2
公开(公告)日：2013-10-01
申请号：US13047097
申请日：2011-03-14
申请人： Srinivasa Rao Banna , Michael A. Van Buskirk , Timothy Thurgate
发明人： Srinivasa Rao Banna , Michael A. Van Buskirk , Timothy Thurgate
IPC分类号： G11C11/34
CPC分类号： H01L27/10802 , G11C7/00 , H01L27/105 , H01L27/1052 , H01L27/1203 , H01L29/0847 , H01L29/1029 , H01L29/1095 , H01L29/7841
摘要： Techniques for providing a semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. Each memory cell including a first region, a a second region, and a body region capacitively coupled to at least one word line and disposed between the first region and the second region. Each memory cell also including a third region, wherein the third region may be doped differently than the first region, the second region, and the body region.
摘要翻译：公开了一种用于提供半导体存储器件的技术。在一个特定示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储器单元的半导体存储器件。每个存储单元包括电容耦合到至少一个字线并且设置在第一区域和第二区域之间的第一区域，第二区域和体区域。每个存储单元还包括第三区域，其中第三区域可以掺杂不同于第一区域，第二区域和体区域。

7. 发明授权

US08315099B2 Techniques for providing a direct injection semiconductor memory device 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US08315099B2
公开(公告)日：2012-11-20
申请号：US12844477
申请日：2010-07-27
申请人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
发明人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
IPC分类号： G11C16/04
CPC分类号： G11C5/02 , G11C5/06 , G11C7/00 , G11C11/402 , G11C16/26 , H01L27/1023 , H01L27/10802 , H01L29/73 , H01L29/7841
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一其他。

8. 发明申请

US20110019482A1 TECHNIQUES FOR PROVIDING A DIRECT INJECTION SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US20110019482A1
公开(公告)日：2011-01-27
申请号：US12844477
申请日：2010-07-27
申请人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
发明人： Michael A. Van Buskirk , Betina Hold , Wayne Ellis
IPC分类号： G11C16/04
CPC分类号： G11C5/02 , G11C5/06 , G11C7/00 , G11C11/402 , G11C16/26 , H01L27/1023 , H01L27/10802 , H01L29/73 , H01L29/7841
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a plurality of memory cells arranged in an array of rows and columns. At least one of the plurality of memory cells may include a first region coupled to a respective bit line of the array and a second region coupled to a respective source line of the array. At least one of the plurality of memory cells may also include a body region spaced apart from and capacitively coupled to a respective word line of the array, wherein the body region may be electrically floating and disposed between the first region and the second region. At least one of the plurality of memory cells may further include a third region coupled to a respective carrier injection line of the array and wherein the respective carrier injection line may be one of a plurality of carrier injection lines in the array that are coupled to each other.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个特定的示例性实施例中，这些技术可以被实现为包括布置成行和列阵列的多个存储单元的直接注入半导体存储器件。多个存储器单元中的至少一个可以包括耦合到阵列的相应位线的第一区域和耦合到阵列的相应源极线的第二区域。多个存储器单元中的至少一个还可以包括与阵列的相应字线间隔开并且电容耦合到阵列的相应字线的主体区域，其中主体区域可以是电浮置的并且设置在第一区域和第二区域之间。多个存储器单元中的至少一个可以进一步包括耦合到阵列的相应载流子注入线的第三区域，并且其中相应的载流子注入管线可以是阵列中耦合到每个的多个载流子注入管线之一其他。

9. 发明授权

US07672161B2 Adaptive detection of threshold levels in memory 失效
标题翻译：内存阈值水平的自适应检测
公开(公告)号：US07672161B2
公开(公告)日：2010-03-02
申请号：US11742371
申请日：2007-04-30
申请人： Ping Hou , Eugen Gershon , Michael A. Van Buskirk
发明人： Ping Hou , Eugen Gershon , Michael A. Van Buskirk
IPC分类号： G11C11/03
CPC分类号： G11C11/5642
摘要： Systems, methods, and/or devices that facilitate accessing data from memory are presented. An adaptive detection component can be employed to reduce or minimize detection error and distinguish information stored in memory cells during read operations. A decoder component can include the adaptive detection component, which can employ an adaptive Linde-Buzo-Gray (LBG) algorithm. The decoder component can receive information associated with a current level from a memory location during a read operation, and can analyze and process such information. The adaptive detection component can receive the processed information and, along with other information, can process such information using the iterative LBG algorithm until reconstruction levels and corresponding threshold levels are determined. Such reconstruction levels and/or threshold levels can be compared to the value associated with the information read from the memory location to determine the data value of the data in the memory location.
摘要翻译：介绍了便于从存储器访问数据的系统，方法和/或设备。可以采用自适应检测部件来减少或最小化检测误差，并且在读取操作期间区分存储在存储器单元中的信息。解码器组件可以包括自适应检测组件，其可以采用自适应林德 - 布佐灰色（LBG）算法。解码器组件可以在读取操作期间从存储器位置接收与当前级别相关联的信息，并且可以分析和处理这样的信息。自适应检测组件可以接收经处理的信息，并且与其他信息一起可以使用迭代LBG算法来处理这样的信息，直到确定重建级别和对应的阈值级别为止。可以将这样的重建级别和/或阈值级别与与从存储器位置读取的信息相关联的值进行比较，以确定存储器位置中的数据的数据值。

10. 发明授权

US06555436B2 Simultaneous formation of charge storage and bitline to wordline isolation 失效
公开(公告)号：US06555436B2
公开(公告)日：2003-04-29
申请号：US10223195
申请日：2002-08-19
申请人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
发明人： Mark T. Ramsbey , Jean Y. Yang , Hidehiko Shiraiwa , Michael A. Van Buskirk , David M. Rogers , Ravi Sunkavalli , Janet Wang , Narbeh Derhacobian , Yider Wu
IPC分类号： H01L21336
CPC分类号： H01L27/11568 , H01L27/105 , H01L27/115 , H01L27/11573 , Y10S438/954 , Y10S438/981
摘要： One aspect of the present invention relates to a method of forming a non-volatile semiconductor memory device, involving the sequential or non-sequential steps of forming a charge trapping dielectric over a substrate, the substrate having a core region and a periphery region; removing at least a portion of the charge trapping dielectric in the periphery region; forming a gate dielectric in the periphery region; forming buried bitlines in the core region; and forming gates in the core region and the periphery region.

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