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1. 发明申请

US20110173577A1 Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields 审中-公开
标题翻译：用于最大化过程敏感电路产量的模式过程调优和设计优化技术
公开(公告)号：US20110173577A1
公开(公告)日：2011-07-14
申请号：US12024390
申请日：2008-02-01
申请人： Ching-Te K. Chuang , Fook-Luen Heng , Rouwaida Kanj , Keunwoo Kim , Jin-Fuw Lee , Saibal Mukhopadhyay , Sani Richard Nassif , Rama Nand Singh
发明人： Ching-Te K. Chuang , Fook-Luen Heng , Rouwaida Kanj , Keunwoo Kim , Jin-Fuw Lee , Saibal Mukhopadhyay , Sani Richard Nassif , Rama Nand Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained.
摘要翻译：提供了改进电路设计和生产的技术。一方面，提供了一种用于虚拟制造过程敏感电路的方法。该方法包括以下步骤。基于电路的物理布局图，获得制造电路的虚拟表示，其考虑了在电路生产过程中可能发生的一个或多个变化。基于质量的度量用于为制造的电路的虚拟表示投影产量。物理布局图和/或生产过程被修改。重复获得，使用和修改步骤，直到达到期望的预计产量。

2. 发明授权

US08217427B2 High density stable static random access memory 有权
标题翻译：高密度稳定的静态随机存取存储器
公开(公告)号：US08217427B2
公开(公告)日：2012-07-10
申请号：US11865780
申请日：2007-10-02
申请人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
发明人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1108 , H01L27/1203 , H01L29/78648 , Y10S257/905
摘要： A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.
摘要翻译：存储电路包括多个位线结构，多个字线结构与多个位线结构相交以形成多个单元位置; 以及位于多个单元位置的多个单元。每个单元在对应的一个字线结构的控制下选择性地耦合到位线结构中的相应一个，并且每个单元又包括具有至少第一n型场效应的逻辑存储元件晶体管和至少第一p型场效应晶体管。所述至少第一n型场效应晶体管形成有尺寸适于减小所述位线结构的电容的相对较厚的掩埋氧化物层，并且所述至少第一p型场效应晶体管形成有较薄的掩埋氧化物层。

3. 发明授权

US08405129B2 Structure for high density stable static random access memory 有权
标题翻译：高密度稳定静态随机存取存储器的结构
公开(公告)号：US08405129B2
公开(公告)日：2013-03-26
申请号：US13450004
申请日：2012-04-18
申请人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
发明人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
IPC分类号： H01L27/105
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1108 , H01L27/1203 , H01L29/78648 , Y10S257/905
摘要： A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.
摘要翻译：一种有形地体现在用于设计，制造或测试集成电路的机器可读介质中的设计结构包括多个位线结构，与所述多个位线结构相交以形成多个单元位置的多个字线结构，以及位于所述多个单元位置处的多个单元，每个所述单元在对应的字线结构的控制下选择性地耦合到对应的位线结构，每个所述单元包括具有至少第一n- 型场效应晶体管和至少第一p型场效应晶体管，其中所述至少第一n型场效应晶体管形成有尺寸适于减小所述位线结构的电容的相对厚的掩埋氧化物层，并且至少所述第一p型场效应晶体管形成有较薄的掩埋氧化物层。

4. 发明申请

US20120205721A1 Design Structure for High Density Stable Static Random Access Memory 有权
标题翻译：高密度稳定静态随机存取存储器的设计结构
公开(公告)号：US20120205721A1
公开(公告)日：2012-08-16
申请号：US13450004
申请日：2012-04-18
申请人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
发明人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jente Benedict Kuang , Hung C. Ngo
IPC分类号： H01L27/105
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1108 , H01L27/1203 , H01L29/78648 , Y10S257/905
摘要： A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit includes a plurality of bit line structures, a plurality of word line structures intersecting said plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at said plurality of cell locations, each of said cells being selectively coupled to a corresponding bit line structure under control of a corresponding word line structure, each of said cells comprising a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor, wherein said at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of said bit line structures, and said at least first p-type field effect transistor is formed with a relatively thin buried oxide layer.
摘要翻译：一种有形地体现在用于设计，制造或测试集成电路的机器可读介质中的设计结构包括多个位线结构，与所述多个位线结构相交以形成多个单元位置的多个字线结构，以及位于所述多个单元位置处的多个单元，每个所述单元在对应的字线结构的控制下选择性地耦合到对应的位线结构，每个所述单元包括具有至少第一n- 型场效应晶体管和至少第一p型场效应晶体管，其中所述至少第一n型场效应晶体管形成有尺寸适于减小所述位线结构的电容的相对厚的掩埋氧化物层，并且至少所述第一p型场效应晶体管形成有较薄的掩埋氧化物层。

5. 发明授权

US07956669B2 High-density low-power data retention power gating with double-gate devices 有权
标题翻译：具有双栅极器件的高密度低功耗数据保持功率门控
公开(公告)号：US07956669B2
公开(公告)日：2011-06-07
申请号：US11106913
申请日：2005-04-15
申请人： Ching-Te K. Chuang , Koushik K. Das , Keunwoo Kim
发明人： Ching-Te K. Chuang , Koushik K. Das , Keunwoo Kim
IPC分类号： H03K17/687
CPC分类号： H01L27/105 , G11C5/14 , H01L27/11 , H01L27/1116 , H01L29/785 , H01L29/78648 , H03K3/356156
摘要： A new power gating structure with robust data retention capability using only one single double-gate device to provide both power gating switch and virtual supply/ground diode clamp functions. The scheme reduces the transistor count, area, and capacitance of the power gating structure, thus improving circuit performance, power, and leakage. The scheme is compared with the conventional power gating structure via mixed-mode physics-based two-dimensional numerical simulations. Analysis of virtual supply/ground bounce for the proposed scheme is also presented.
摘要翻译：具有强大数据保持能力的新型电源门控结构，仅使用一个单栅极器件来提供电源门控开关和虚拟电源/接地二极管钳位功能。该方案降低了电源门控结构的晶体管数量，面积和电容，从而提高了电路性能，功率和泄漏。该方案通过基于混合模式物理的二维数值模拟与常规电力门控结构进行比较。还提出了拟议方案的虚拟供应/地面反弹分析。

6. 发明申请

US20090302354A1 High Density Stable Static Random Access Memory 有权
标题翻译：高密度稳定静态随机存取存储器
公开(公告)号：US20090302354A1
公开(公告)日：2009-12-10
申请号：US11865780
申请日：2007-10-02
申请人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jante Benedict Kuang , Hung C. Ngo
发明人： Ching-Te K. Chuang , Fadi H. Gebara , Keunwoo Kim , Jante Benedict Kuang , Hung C. Ngo
IPC分类号： H01L27/11
CPC分类号： H01L27/11 , H01L27/0207 , H01L27/1108 , H01L27/1203 , H01L29/78648 , Y10S257/905
摘要： A memory circuit includes a plurality of bit line structures, a plurality of word line structures intersecting the plurality of bit line structures to form a plurality of cell locations; and a plurality of cells located at the plurality of cell locations. Each of the cells is selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures, and each of the cells in turn includes a logical storage element having at least a first n-type field effect transistor and at least a first p-type field effect transistor. The at least first n-type field effect transistor is formed with a relatively thick buried oxide layer sized to reduce capacitance of the bit line structures, and the at least first p-type field effect transistor is formed with a relatively thin buried oxide layer
摘要翻译：存储电路包括多个位线结构，多个字线结构与多个位线结构相交以形成多个单元位置; 以及位于多个单元位置的多个单元。每个单元在对应的一个字线结构的控制下选择性地耦合到位线结构中的相应一个，并且每个单元又包括具有至少第一n型场效应的逻辑存储元件晶体管和至少第一p型场效应晶体管。所述至少第一n型场效应晶体管形成有尺寸适于减小位线结构的电容的相对较厚的掩埋氧化物层，并且所述至少第一p型场效应晶体管形成有相对较薄的掩埋氧化物层

7. 发明申请

US20130289965A1 FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING 有权
公开(公告)号：US20130289965A1
公开(公告)日：2013-10-31
申请号：US13457722
申请日：2012-04-27
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

8. 发明申请

US20130289948A1 FET-BOUNDING FOR FAST TCAD-BASED VARIATION MODELING 有权
标题翻译：基于快速TCAD变换建模的场效应晶体管
公开(公告)号：US20130289948A1
公开(公告)日：2013-10-31
申请号：US13611359
申请日：2012-09-12
申请人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
发明人： Rajiv V. Joshi , Rouwaida N. Kanj , Keunwoo Kim
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.
摘要翻译：一种用于分析电路的方法包括识别完整设备结构中的一个或多个设备区域。设备区域提供要分析的感兴趣区域。生成代表性地包括一个或多个设备区域的部分设备。通过采用整个装置结构的物理特性来减少部分装置的分析网格。使用处理器来模拟部分设备，以获得代表整个设备结构的感兴趣区域中的设备输出信息。还披露了系统。

9. 发明授权

US07742327B2 Computer-readable medium encoding a back-gate controlled asymmetrical memory cell and memory using the cell 失效
标题翻译：使用该单元编码背栅控制的非对称存储单元和存储器的计算机可读介质
公开(公告)号：US07742327B2
公开(公告)日：2010-06-22
申请号：US12265042
申请日：2008-11-05
申请人： Ching Te Chuang , Jae-Joon Kim , Keunwoo Kim
发明人： Ching Te Chuang , Jae-Joon Kim , Keunwoo Kim
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , G11C11/413
摘要： Techniques are provided for back-gate control in an asymmetrical memory cell. In one aspect, the cell includes five transistors and can be employed for static random access memory (SRAM) applications. An inventive memory circuit can include a plurality of bit line structures, a plurality of word line structures that intersect the plurality of bit line structures to form a plurality of cell locations, and a plurality of cells located at the plurality of cell locations. Each cell can be selectively coupled to a corresponding one of the bit line structures under control of a corresponding one of the word line structures. Each cell can include a first inverter having first and second field effect transistors (FETS) and a second inverter with third and fourth FETS that is cross-coupled to the first inverter to form a storage flip-flop. One of the FETS in the first inverter can be configured with independent front and back gates and can function as both an access transistor and part of one of the inverters.
摘要翻译：为非对称存储单元中的背栅极控制提供技术。在一个方面，电池包括五个晶体管，并且可以用于静态随机存取存储器（SRAM）应用。本发明的存储器电路可以包括多个位线结构，与多个位线结构相交以形成多个单元位置的多个字线结构以及位于多个单元位置的多个单元。每个单元可以在对应的一个字线结构的控制下选择性地耦合到相应的一个位线结构。每个单元可以包括具有第一和第二场效应晶体管（FETS）的第一反相器和具有与第一反相器交叉耦合以形成存储触发器的第三和第四FET的第二反相器。第一反相器中的FETS之一可以配置有独立的前门和后门，并且可以用作存取晶体管和其中一个逆变器的一部分。

10. 发明授权

US07532501B2 Semiconductor device including back-gated transistors and method of fabricating the device 有权
标题翻译：包括后门控晶体管的半导体器件及其制造方法
公开(公告)号：US07532501B2
公开(公告)日：2009-05-12
申请号：US11142248
申请日：2005-06-02
申请人： Rajiv V. Joshi , Keunwoo Kim , Edward Joseph Nowak , Richard Quimby Williams
发明人： Rajiv V. Joshi , Keunwoo Kim , Edward Joseph Nowak , Richard Quimby Williams
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L29/66795 , H01L29/785
摘要： A memory cell (e.g., static random access memory (SRAM) cell) includes a plurality of back-gated n-type field effect transistors (nFETs), and a plurality of double-gated p-type field effect transistors (pFETs) operatively coupled to the plurality of nFETs.
摘要翻译：存储器单元（例如，静态随机存取存储器（SRAM）单元）包括多个后门控n型场效应晶体管（nFET）和多个双门控p型场效应晶体管（pFET），可操作地耦合到多个nFET。

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