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1. 发明授权

US08112729B2 Method and system for selective stress enablement in simulation modeling 有权
标题翻译：模拟建模中选择性应力启用的方法和系统
公开(公告)号：US08112729B2
公开(公告)日：2012-02-07
申请号：US12426342
申请日：2009-04-20
申请人： William Robert Tonti , Richard Quimby Williams
发明人： William Robert Tonti , Richard Quimby Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5009
摘要： A method and system for modeling an integrated circuit. The method includes converting a representation of the integrated circuit into design shapes of design levels of a design of the integrated circuit; adding control shapes to the design, the control shapes not defining any physical part of the integrated circuit; extracting layout-dependent stress parameters of the devices from the design levels of the design based on the control shapes and the design shapes; converting the layout-dependent stress parameters to stress parameters using a stress algorithm; generating stressed device parameters from the stress parameters using a compact model; and simulating performance of the integrated circuit using the stressed device parameters in a simulation model of the integrated circuit design.
摘要翻译：一种集成电路建模方法和系统。该方法包括将集成电路的表示转换为集成电路设计的设计级别的设计形状; 将控制形状添加到设计中，控制形状不限定集成电路的任何物理部分; 基于控制形状和设计形状，从设计的设计级别提取设备的布局相关应力参数; 使用应力算法将布局依赖应力参数转换为应力参数; 使用紧凑型模型从应力参数产生应力器件参数; 并在集成电路设计的仿真模型中使用应力器件参数来模拟集成电路的性能。

2. 发明授权

US07532501B2 Semiconductor device including back-gated transistors and method of fabricating the device 有权
标题翻译：包括后门控晶体管的半导体器件及其制造方法
公开(公告)号：US07532501B2
公开(公告)日：2009-05-12
申请号：US11142248
申请日：2005-06-02
申请人： Rajiv V. Joshi , Keunwoo Kim , Edward Joseph Nowak , Richard Quimby Williams
发明人： Rajiv V. Joshi , Keunwoo Kim , Edward Joseph Nowak , Richard Quimby Williams
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , H01L27/0207 , H01L27/11 , H01L27/1104 , H01L29/66795 , H01L29/785
摘要： A memory cell (e.g., static random access memory (SRAM) cell) includes a plurality of back-gated n-type field effect transistors (nFETs), and a plurality of double-gated p-type field effect transistors (pFETs) operatively coupled to the plurality of nFETs.
摘要翻译：存储器单元（例如，静态随机存取存储器（SRAM）单元）包括多个后门控n型场效应晶体管（nFET）和多个双门控p型场效应晶体管（pFET），可操作地耦合到多个nFET。

3. 发明授权

US06397380B1 Computer-program compilers comprising a program augmentation capability 失效
标题翻译：包括程序增强功能的计算机程序编译器
公开(公告)号：US06397380B1
公开(公告)日：2002-05-28
申请号：US08634515
申请日：1996-04-18
申请人： Calvin John Bittner , Bertrand M. Grossman , Richard Dimick Jenks , Stephen Michael Watt , Richard Quimby Williams
发明人： Calvin John Bittner , Bertrand M. Grossman , Richard Dimick Jenks , Stephen Michael Watt , Richard Quimby Williams
IPC分类号： G06F945
CPC分类号： G06F8/443
摘要： A method for optimizing and transforming a compiler program in a computer system. The method comprises the steps of constructing a compiler comprising a program augmentation capability; and, locating this capability in association with phases of a standard compilation process. The program augmentation capability may comprise symbolic automatic differentiation, or generation of Taylor series, or generation of Hessian or Jacobian matrices.
摘要翻译：一种用于优化和转换计算机系统中的编译程序的方法。该方法包括以下步骤：构建包括程序增强能力的编译器; 并将此功能与标准编译过程的阶段相关联。程序增强能力可以包括符号自动区分，或者产生泰勒级数，或者生成黑森或雅可比矩阵。

4. 发明授权

US06223341B1 Computer-program compilers comprising a program augmentation capability 失效
标题翻译：包括程序增强功能的计算机程序编译器
公开(公告)号：US06223341B1
公开(公告)日：2001-04-24
申请号：US09071115
申请日：1998-05-01
申请人： Calvin John Bittner , Bertrand M. Grossman , Richard Dimick Jenks , Stephen Michael Watt , Richard Quimby Williams
发明人： Calvin John Bittner , Bertrand M. Grossman , Richard Dimick Jenks , Stephen Michael Watt , Richard Quimby Williams
IPC分类号： G06F945
CPC分类号： G06F8/443
摘要： A method for optimizing and transforming a compiler program in a computer system. The method comprises the steps of constructing a compiler comprising a program augmentation capability; and, locating this capability in association with phases of a standard compilation process. The program augmentation capability may comprise symbolic automatic differentiation, or generation of Taylor series, or generation of Hessian or Jacobian matrices.
摘要翻译：一种用于优化和转换计算机系统中的编译程序的方法。该方法包括以下步骤：构建包括程序增强能力的编译器; 并将此功能与标准编译过程的阶段相关联。程序增强能力可以包括符号自动区分，或者产生泰勒级数，或者生成黑森或雅可比矩阵。

5. 发明申请

US20100269075A1 METHOD AND SYSTEM FOR SELECTIVE STRESS ENABLEMENT IN SIMULATION MODELING 有权
标题翻译：模拟建模中选择应力应变的方法与系统
公开(公告)号：US20100269075A1
公开(公告)日：2010-10-21
申请号：US12426342
申请日：2009-04-20
申请人： William Robert Tonti , Richard Quimby Williams
发明人： William Robert Tonti , Richard Quimby Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5009
摘要： A method and system for modeling an integrated circuit. The method includes converting a representation of the integrated circuit into design shapes of design levels of a design of the integrated circuit; adding control shapes to the design, the control shapes not defining any physical part of the integrated circuit; extracting layout-dependent stress parameters of the devices from the design levels of the design based on the control shapes and the design shapes; converting the layout-dependent stress parameters to stress parameters using a stress algorithm; generating stressed device parameters from the stress parameters using a compact model; and simulating performance of the integrated circuit using the stressed device parameters in a simulation model of the integrated circuit design.
摘要翻译：一种集成电路建模方法和系统。该方法包括将集成电路的表示转换为集成电路设计的设计级别的设计形状; 将控制形状添加到设计中，控制形状不限定集成电路的任何物理部分; 基于控制形状和设计形状，从设计的设计级别提取设备的布局相关应力参数; 使用应力算法将布局依赖应力参数转换为应力参数; 使用紧凑型模型从应力参数产生应力器件参数; 并在集成电路设计的仿真模型中使用应力器件参数来模拟集成电路的性能。

6. 发明授权

US07250351B2 Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors 失效
标题翻译：增强的绝缘体上硅（SOI）晶体管和制造增强型SOI晶体管的方法
公开(公告)号：US07250351B2
公开(公告)日：2007-07-31
申请号：US11106002
申请日：2005-04-14
申请人： Toshiharu Furukawa , Carl John Radens , William Robert Tonti , Richard Quimby Williams
发明人： Toshiharu Furukawa , Carl John Radens , William Robert Tonti , Richard Quimby Williams
IPC分类号： H01L29/76
CPC分类号： H01L29/78687 , H01L21/26533 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/66772 , H01L29/7842 , H01L29/7848 , H01L29/78603
摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.
摘要翻译：提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。

7. 发明授权

US6063132A Method for verifying design rule checking software 失效
标题翻译：验证设计规则检查软件的方法
公开(公告)号：US6063132A
公开(公告)日：2000-05-16
申请号：US105731
申请日：1998-06-26
申请人： William Frantz DeCamp , Laurice Thorsen Earl , Jason Steven Minahan , James Robert Montstream , Daniel John Nickel , Joseph James Oler, Jr. , Richard Quimby Williams
发明人： William Frantz DeCamp , Laurice Thorsen Earl , Jason Steven Minahan , James Robert Montstream , Daniel John Nickel , Joseph James Oler, Jr. , Richard Quimby Williams
IPC分类号： G06F17/50 , G06F15/18
CPC分类号： G06F17/5081
摘要： A method using a generate-and-verify computer program product to generate by repetitive passes a design rules checking computer program, wherein the design rules are described in a file called a runset. The design rules checking program is used for exhaustive testing of VLSI chips for compliance to the design rules of a given VLSI fabrication process. The runset is repeatedly iterated in loop fashion with respect to a testcase file containing groups of layout structures or shapes used for verifying the correctness of the runset. A general purpose shapes processing program creates an error shapes file for storing geometrical errors found in each said layout structure. Two additional shapes are used in the verification process: user boundary shapes for defining areas in which errors are not to be detected for a given design rule, and automated boundary shapes created to surround each said layout structure with a boundary that defines regions where error shapes can occur. An association table is created which is a compilation of the error shapes, user boundary shapes, and automated boundary shapes associated with each layout structure. The association table is processed to determine the correctness of the runset. The runset is modified to correct each valid error. The repetitive passes continue until a final runset is generated. This final runset becomes the input to design rules checking computer program product and customizes the program for a given VLSI fabrication process.
摘要翻译：一种使用生成和验证计算机程序产品通过重复传递生成设计规则检查计算机程序的方法，其中设计规则在称为runset的文件中描述。设计规则检查程序用于VLSI芯片的详尽测试，以符合给定的VLSI制造工艺的设计规则。相对于包含用于验证运行集合的正确性的布局结构或形状的组的测试用例文件，运行环以循环方式重复迭代。通用形状处理程序创建用于存储在每个所述布局结构中发现的几何错误的错误形状文件。在验证过程中使用两种额外的形状：用于定义不能针对给定设计规则检测错误的区域的用户边界形状，以及围绕每个所述布局结构创建的自动边界形状，其边界限定了错误形状可以发生。创建关联表，其是与每个布局结构相关联的错误形状，用户边界形状和自动边界形状的汇编。处理关联表以确定运行集的正确性。修改运行集以更正每个有效错误。重复的传递将继续，直到生成最后的运行。这个最终的运行成为设计规则检查计算机程序产品的输入，并为给定的VLSI制造过程定制程序。

8. 发明授权

US07129138B1 Methods of implementing and enhanced silicon-on-insulator (SOI) box structures 失效
标题翻译：实现和增强绝缘体上硅（SOI）盒结构的方法
公开(公告)号：US07129138B1
公开(公告)日：2006-10-31
申请号：US11106004
申请日：2005-04-14
申请人： Toshiharu Furukawa , Carl John Radens , William Robert Tonti , Richard Quimby Williams
发明人： Toshiharu Furukawa , Carl John Radens , William Robert Tonti , Richard Quimby Williams
IPC分类号： H01L21/762
CPC分类号： H01L29/66772 , H01L21/84 , H01L23/5252 , H01L27/1203 , H01L2924/0002 , Y10S438/928 , H01L2924/00
摘要： Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices.
摘要翻译：提供了增强的绝缘体上硅（SOI）掩埋氧化物（BOX）结构和方法来实现增强的SOI BOX结构。将氧注入步骤从背面进行到薄化的硅衬底层。退火步骤从硅衬底层中的氧注入形成厚的掩埋氧化物（BOX）区域。氧注入步骤在氧植入物附近形成隔离区域。背侧注入步骤选择性地掺杂用于形成包括所选择的抗熔丝（AF）器件的SOI器件的SOI器件的隔离区域以及包括PFET和NFET器件的SOI晶体管的隔离区域。

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