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1. 发明授权

US08539421B2 Layout-specific classification and prioritization of recommended rules violations 有权
标题翻译：布局特定的分类和推荐规则违规的优先级排序
公开(公告)号：US08539421B2
公开(公告)日：2013-09-17
申请号：US13328942
申请日：2011-12-16
申请人： Kanak Behari Agarwal , Sani Richard Nassif
发明人： Kanak Behari Agarwal , Sani Richard Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method, system, and computer program product for classifying and prioritizing a set of recommended rule (RR) violations in an integrated circuit (IC) design are provided in the illustrative embodiments. The set of RR violations is received. A layout corresponding to the IC design is received. A set of features is selected in the layout. A classification model corresponding to the set of features is selected. Using the set of features and the classification model, the first RR violation is classified into a classification from a set of classifications. The classification is prioritized in an order of priority such that the first RR violation in the classification is recommended for remedying in the order of priority.
摘要翻译：在说明性实施例中提供了用于在集成电路（IC）设计中对一组推荐规则（RR）违规进行分类和优先排序的方法，系统和计算机程序产品。接收到RR违规的集合。接收与IC设计对应的布局。在布局中选择一组功能。选择与特征集对应的分类模型。使用一组特征和分类模型，将第一个RR违规分为一组分类的分类。分类按优先顺序排列优先顺序，以便按照优先顺序推荐分类中的第一次违反RR的行为。

2. 发明申请

US20110173577A1 Techniques for Pattern Process Tuning and Design Optimization for Maximizing Process-Sensitive Circuit Yields 审中-公开
标题翻译：用于最大化过程敏感电路产量的模式过程调优和设计优化技术
公开(公告)号：US20110173577A1
公开(公告)日：2011-07-14
申请号：US12024390
申请日：2008-02-01
申请人： Ching-Te K. Chuang , Fook-Luen Heng , Rouwaida Kanj , Keunwoo Kim , Jin-Fuw Lee , Saibal Mukhopadhyay , Sani Richard Nassif , Rama Nand Singh
发明人： Ching-Te K. Chuang , Fook-Luen Heng , Rouwaida Kanj , Keunwoo Kim , Jin-Fuw Lee , Saibal Mukhopadhyay , Sani Richard Nassif , Rama Nand Singh
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F2217/10
摘要： Techniques for improving circuit design and production are provided. In one aspect, a method for virtual fabrication of a process-sensitive circuit is provided. The method comprises the following steps. Based on a physical layout diagram of the circuit, a virtual representation of the fabricated circuit is obtained that accounts for one or more variations that can occur during a circuit production process. A quality-based metric is used to project a production yield for the virtual representation of the fabricated circuit. The physical layout diagram and/or the production process are modified. The obtaining, using and modifying steps are repeated until a desired projected production yield is attained.
摘要翻译：提供了改进电路设计和生产的技术。一方面，提供了一种用于虚拟制造过程敏感电路的方法。该方法包括以下步骤。基于电路的物理布局图，获得制造电路的虚拟表示，其考虑了在电路生产过程中可能发生的一个或多个变化。基于质量的度量用于为制造的电路的虚拟表示投影产量。物理布局图和/或生产过程被修改。重复获得，使用和修改步骤，直到达到期望的预计产量。

3. 发明授权

US06898769B2 Decoupling capacitor sizing and placement 失效
标题翻译：去耦电容器尺寸和放置
公开(公告)号：US06898769B2
公开(公告)日：2005-05-24
申请号：US10268236
申请日：2002-10-10
申请人： Sani Richard Nassif , Haihua Su
发明人： Sani Richard Nassif , Haihua Su
IPC分类号： G06F17/50
CPC分类号： G06F17/5072
摘要： A method and system for reducing noise in a power grid of an integrated circuit, which optimizes the placement and sizing of decoupling capacitors in the power grid. Logic cells are located in a first layout of the integrated circuit with empty spaces between the adjacent cells, and the placement of the cells is changed to a second layout wherein the size of the empty spaces between the adjacent cells also change. The decoupling capacitors are placed in the empty spaces of the second layout. In the example of a row-oriented cell structure, the empty spaces may be uniformly distributed along each row for the initial layout. An adjoint sensitivity analysis is performed of the sensitivity of a noise function of the integrated circuit with respect to sizes of the empty spaces between adjacent cells, and an original noise waveform is convolved with an adjoint noise waveform. The convolution may use piecewise linear compressions of the original and adjoint noise waveforms. A quadratic programming solver is then used to iteratively determine the sizes of the empty spaces between adjacent cells.
摘要翻译：一种用于降低集成电路电网噪声的方法和系统，其优化了电网中去耦电容器的布局和尺寸。逻辑单元位于集成电路的第一布局中，在相邻单元之间具有空白空间，并且单元的布置被改变为第二布局，其中相邻单元之间的空白空间的大小也改变。去耦电容器被放置在第二布局的空的空间中。在面向行的单元结构的示例中，空格可以沿着每一行均匀地分布用于初始布局。执行集成电路的噪声功能相对于相邻小区之间的空白空间的大小的灵敏度的伴随灵敏度分析，原始噪声波形与伴随噪声波形卷积。卷积可以使用原始和伴随噪声波形的分段线性压缩。然后使用二次规划求解器来迭代地确定相邻单元之间的空白空间的大小。

4. 发明授权

US08914272B2 Visualizing sensitivity information in integrated circuit design 有权
标题翻译：集成电路设计中可视化灵敏度信息
公开(公告)号：US08914272B2
公开(公告)日：2014-12-16
申请号：US13325244
申请日：2011-12-14
申请人： Anne Elizabeth Gattiker , Sani Richard Nassif
发明人： Anne Elizabeth Gattiker , Sani Richard Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F2217/12 , G06F2217/74 , Y02P90/265
摘要： A method, system, and computer program product for visualizing sensitivity information in integrated circuit (IC) design are provided in the illustrative embodiments. A plurality of sensitivity information corresponding to a first component in the IC design is received, wherein the plurality of sensitivity information includes a first sensitivity information indicating a first variation in a first electrical characteristic of a group of components as a result of a variation in an electrical characteristic of the first component. A plurality of aspects of the first sensitivity information are rendered in visual form to form a first visualization. The first visualization is presented on a schematic view of the IC design in an IC design tool such that the first sensitivity information is visually associated with the first component in the IC design.
摘要翻译：在说明性实施例中提供了用于在集成电路（IC）设计中可视化灵敏度信息的方法，系统和计算机程序产品。接收对应于IC设计中的第一分量的多个灵敏度信息，其中所述多个灵敏度信息包括第一灵敏度信息，所述第一灵敏度信息指示作为一组变化的结果的一组分量的第一电特性中的第一变化第一部件的电气特性。第一灵敏度信息的多个方面以视觉形式呈现以形成第一可视化。第一个可视化在IC设计工具中的IC设计的示意图上呈现，使得第一灵敏度信息在视觉上与IC设计中的第一个组件相关联。

5. 发明授权

US08595664B2 Guiding design actions for complex failure modes 失效
标题翻译：指导复杂故障模式的设计动作
公开(公告)号：US08595664B2
公开(公告)日：2013-11-26
申请号：US13328911
申请日：2011-12-16
申请人： Anne Elizabeth Gattiker , Sani Richard Nassif
发明人： Anne Elizabeth Gattiker , Sani Richard Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081 , G06F2217/10 , G06F2217/70
摘要： A system, and computer program product for guiding design actions for complex failure modes in an integrated circuit (IC) design are provided in the illustrative embodiments. A probability of failure estimate of a circuit according to the IC design is received, the probability being determined using a simulation. A sensitivity of the probability of failure to a variable associated with a component in the circuit is calculated, wherein the sensitivity is determined by an estimation without the simulation. The sensitivity is depicted relative to the component in the IC design such that the sensitivity is associated with the component and a visual relationship between the component and the sensitivity is usable for adjusting a characteristic of the component to reduce the probability of failure of the circuit.
摘要翻译：在说明性实施例中提供了用于在集成电路（IC）设计中引导复杂故障模式的设计动作的系统和计算机程序产品。接收到根据IC设计的电路的故障估计概率，使用仿真确定概率。计算故障概率对与电路中的部件相关联的变量的敏感度，其中灵敏度由没有模拟的估计确定。相对于IC设计中的部件来说明灵敏度，使得灵敏度与部件相关联，并且部件和灵敏度之间的视觉关系可用于调整部件的特性以降低电路故障的可能性。

6. 发明申请

US20130159955A1 DYNAMIC PIN ACCESS MAXIMIZATION FOR MULTI-PATTERNING LITHOGRAPHY 审中-公开
标题翻译：用于多格式平移的动态引脚访问最大化
公开(公告)号：US20130159955A1
公开(公告)日：2013-06-20
申请号：US13328976
申请日：2011-12-16
申请人： Rani Abou Ghaida , Kanak Behari Agarwal , Lars Wolfgang Liebmann , Sani Richard Nassif
发明人： Rani Abou Ghaida , Kanak Behari Agarwal , Lars Wolfgang Liebmann , Sani Richard Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G06F17/5081
摘要： A method, system, and computer program product for improving pin access in a design of an integrated circuit (IC) for multi-patterning lithography (MPL) are provided in the illustrative embodiments. A cell is placed in the IC design, the cell including a pin shape configured to connect a pin of the cell to a semi-conductor component in the IC design, the cell including a coloring conflict due to the pin shape and an other shape in the cell each being colored using a first color for fabricating onto a wafer using MPL. A net is routed to the pin shape without resolving the coloring conflict, wherein the routing routes the net using a first segment of the pin shape. The pin shape is modified after routing to resolve the coloring conflict to result in a modified cell.
摘要翻译：在说明性实施例中提供了用于在用于多图案化光刻（MPL）的集成电路（IC）的设计中改善引脚访问的方法，系统和计算机程序产品。电池被放置在IC设计中，电池包括被配置为将电池的引脚连接到IC设计中的半导体部件的引脚形状，该电池包括由于引脚形状引起的着色冲突和其他形状每个单元均使用第一种颜色进行着色，以使用MPL制造到晶片上。网络被路由到引脚形状而不解决着色冲突，其中，路由使用引脚形状的第一段路由网络。引脚形状在路由后修改以解决着色冲突，从而导致修改的单元格。

7. 发明申请

US20130159948A1 LAYOUT-SPECIFIC CLASSIFICATION AND PRIORITIZATION OF RECOMMENDED RULES VIOLATIONS 有权
标题翻译：建议的规则侵权的布局特定分类和优先
公开(公告)号：US20130159948A1
公开(公告)日：2013-06-20
申请号：US13328942
申请日：2011-12-16
申请人： Kanak Behari Agarwal , Sani Richard Nassif
发明人： Kanak Behari Agarwal , Sani Richard Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5081
摘要： A method, system, and computer program product for classifying and prioritizing a set of recommended rule (RR) violations in an integrated circuit (IC) design are provided in the illustrative embodiments. The set of RR violations is received. A layout corresponding to the IC design is received. A set of features is selected in the layout. A classification model corresponding to the set of features is selected. Using the set of features and the classification model, the first RR violation is classified into a classification from a set of classifications. The classification is prioritized in an order of priority such that the first RR violation in the classification is recommended for remedying in the order of priority.
摘要翻译：在说明性实施例中提供了用于在集成电路（IC）设计中对一组推荐规则（RR）违规进行分类和优先排序的方法，系统和计算机程序产品。接收到RR违规的集合。接收与IC设计对应的布局。在布局中选择一组功能。选择与特征集对应的分类模型。使用一组特征和分类模型，将第一个RR违规分为一组分类的分类。分类按优先顺序排列优先顺序，以便按照优先顺序推荐分类中的第一次违反RR的行为。

8. 发明申请

US20130159947A1 GUIDING DESIGN ACTIONS FOR COMPLEX FAILURE MODES 失效
标题翻译：指导复杂故障模式的设计措施
公开(公告)号：US20130159947A1
公开(公告)日：2013-06-20
申请号：US13460369
申请日：2012-04-30
申请人： ANNE ELIZABETH GATTIKER , Sani Richard Nassif
发明人： ANNE ELIZABETH GATTIKER , Sani Richard Nassif
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5081 , G06F2217/10 , G06F2217/70
摘要： A method for guiding design actions for complex failure modes in an integrated circuit (IC) design is provided in the illustrative embodiments. A probability of failure estimate of a circuit according to the IC design is received, the probability being determined using a simulation. A sensitivity of the probability of failure to a variable associated with a component in the circuit is calculated, wherein the sensitivity is determined by an estimation without the simulation. The sensitivity is depicted relative to the component in the IC design such that the sensitivity is associated with the component and a visual relationship between the component and the sensitivity is usable for adjusting a characteristic of the component to reduce the probability of failure of the circuit.
摘要翻译：在说明性实施例中提供了用于在集成电路（IC）设计中引导复杂故障模式的设计动作的方法。接收到根据IC设计的电路的故障估计概率，使用仿真确定概率。计算故障概率对与电路中的部件相关联的变量的敏感度，其中灵敏度由没有模拟的估计确定。相对于IC设计中的部件来说明灵敏度，使得灵敏度与部件相关联，并且部件和灵敏度之间的视觉关系可用于调整部件的特性以降低电路故障的可能性。

9. 发明授权

US06754092B2 Method and apparatus for reducing power consumption for power supplied by a voltage adapter 失效
公开(公告)号：US06754092B2
公开(公告)日：2004-06-22
申请号：US10185707
申请日：2002-06-27
申请人： Chandler Todd McDowell , Sani Richard Nassif
发明人： Chandler Todd McDowell , Sani Richard Nassif
IPC分类号： H02M704
CPC分类号： G06F1/28 , G06F1/263 , G06F1/3203 , H02M2001/0032 , Y02B70/16 , Y10T307/469
摘要： Power consumption is reduced for power supplied by a voltage adapter, such as an AC/DC adapter. A power source is connected to a power unit, including the voltage adapter and control circuitry. The voltage adapter supplies power to a load, such as a computer system. A load current supplied by the voltage adapter and an output voltage of the voltage adapter are measured by the control circuitry, and a control device of the control circuitry selectively disconnects the voltage adapter from the power source. The disconnecting is responsive to the control circuitry inferring from the measured current and voltage that the load is turned off, or at least operating in a reduced power consumption mode.

10. 发明授权

US06731129B1 Apparatus for measuring capacitance of a semiconductor device 失效
标题翻译：用于测量半导体器件的电容的装置
公开(公告)号：US06731129B1
公开(公告)日：2004-05-04
申请号：US10322074
申请日：2002-12-17
申请人： Wendy Ann Belluomini , Chandler Todd McDowell , Sani Richard Nassif , Ying Liu
发明人： Wendy Ann Belluomini , Chandler Todd McDowell , Sani Richard Nassif , Ying Liu
IPC分类号： G01R3128
CPC分类号： G01R27/2605
摘要： An apparatus for measuring capacitance of a semiconductor device is disclosed. The apparatus includes a signal source circuit, a first transistor, a second transistor, and bypass capacitor. The first transistor is connected in series with the second transistor, and the second transistor is connected in series with a device under test. The bypass capacitor connected in parallel with the first and second transistors. Coupled to the first and second transistors, the signal source circuit generates a first signal and a second signal to alternately turn on said first and second transistors such that a discharge current is generated to flow through the first and second transistors.
摘要翻译：公开了一种用于测量半导体器件的电容的装置。该装置包括信号源电路，第一晶体管，第二晶体管和旁路电容器。第一晶体管与第二晶体管串联连接，第二晶体管与被测器件串联连接。旁路电容器与第一和第二晶体管并联连接。耦合到第一和第二晶体管，信号源电路产生第一信号和第二信号以交替地接通所述第一和第二晶体管，使得产生放电电流以流过第一和第二晶体管。

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